74AHC_AHCT1G86_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 4 July 2007 6 of 12
NXP Semiconductors
74AHC1G86; 74AHCT1G86
2-input EXCLUSIVE-OR gate
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] Typical values are measured at V
CC
= 3.3 V.
[3] Typical values are measured at V
CC
= 5.0 V.
[4] C
PD
is used to determine the dynamic power dissipation P
D
(µW).
P
D
=C
PD
× V
CC
2
× f
i
+ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
12. Waveforms
For type 74AHCT1G86
t
pd
propagation
delay
A and B to Y
[1]
V
CC
= 4.5 V to 5.5 V
[3]
C
L
= 15 pF - 3.5 6.9 1.0 8.0 1.0 9.0 ns
C
L
= 50 pF - 5.0 7.9 1.0 9.0 1.0 10.5 ns
C
PD
power
dissipation
capacitance
per buffer;
C
L
=50pF;f=1 MHz;
V
I
= GND to V
CC
[4]
-11- - - - - pF
Table 8. Dynamic characteristics
…continued
GND = 0 V; t
r
= t
f
=
3.0 ns. For waveform see Figure 5. For test circuit see Figure 6.
Symbol Parameter Conditions 25 °C 40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 9.
Fig 5. The input (A and B) to output (Y) propagation delays
mna041
t
PHL
t
PLH
V
M
V
M
A, B
input
Y
output
Table 9. Measurement points
Type Input Output
V
I
V
M
V
M
74AHC1G86 GND to V
CC
0.5 × V
CC
0.5 × V
CC
74AHCT1G86 GND to 3.0 V 1.5 V 0.5 × V
CC
74AHC_AHCT1G86_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 4 July 2007 7 of 12
NXP Semiconductors
74AHC1G86; 74AHCT1G86
2-input EXCLUSIVE-OR gate
Test data is given in Table 8. Definitions for test circuit:
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 6. Load circuitry for switching times
V
CC
V
I
V
O
mna034
DUT
C
L
50 pF
R
T
PULSE
GENERATOR
74AHC_AHCT1G86_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 4 July 2007 8 of 12
NXP Semiconductors
74AHC1G86; 74AHCT1G86
2-input EXCLUSIVE-OR gate
13. Package outline
Fig 7. Package outline SOT353-1 (TSSOP5)
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
wyv
ceD
(1)
E
(1)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
0.65
e
1
1.3
2.25
2.0
0.60
0.15
7°
0°
0.1 0.10.30.425
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.46
0.21
SOT353-1 MO-203 SC-88A
00-09-01
03-02-19
w M
b
p
D
Z
e
e
1
0.15
13
5
4
θ
A
A
2
A
1
L
p
(A
3
)
detail X
L
H
E
E
c
v M
A
X
A
y
1.5 3 mm0
scale
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
1.1

74AHCT1G86GW,125

Mfr. #:
Manufacturer:
Nexperia
Description:
Logic Gates EXCLUSIVE OR GATE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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