MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
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Chip-Enable Signal Gating
The MAX792/MAX820 provide internal gating of chip-
enable (CE) signals, which prevents erroneous data
from corrupting CMOS RAM in the event of an under-
voltage condition. The MAX792/MAX820 use a series
transmission gate from
CE
IN to
CE
OUT (Figure 1).
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transi-
tions. When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting the
CMOS RAM. The 10ns max CE propagation delay from
CE
IN to
CE
OUT enables the MAX792/MAX820 to be
used with most µPs. If
CE
IN is low when reset asserts,
CE
OUT remains low for a short period to permit com-
pletion of the current write cycle.
Chip-Enable Input
The CE transmission gate is disabled and
CE
IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when V
CC
passes the
reset threshold, the CE transmission gate disables and
CE
IN immediately becomes high impedance if the volt-
age at
CE
IN is high. If
CE
IN is low when reset is assert-
ed, the CE transmission gate will disable at the moment
CE
IN goes high or 15µs after reset is asserted,
whichever occurs first (Figure 9). This permits the cur-
rent write cycle to complete during power-down.
During a power-up sequence, the CE transmission gate
remains disabled and
CE
IN remains high impedance
regardless of
CE
IN activity, until reset is deasserted fol-
lowing the reset timeout period.
While disabled,
CE
IN is high impedance. When the CE
transmission gate is enabled, the impedance of
CE
IN
will appear as a 75Ω (V
CC
= 5V) resistor in series with
the load at
CE
OUT.
The propagation delay through the CE transmission
gate depends on V
CC,
the source impedance of the
drive connected to
CE
IN, and the loading on
CE
OUT
(see the Chip-Enable Propagation Delay vs.
CE
OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on
CE
IN to the 50%
point on
CE
OUT using a 50Ω driver and 50pF of load
capacitance (Figure 10). For minimum propagation
delay, minimize the capacitive load at
CE
OUT, and use
a low-output-impedance driver.
Chip-Enable Output
When the CE transmission gate is enabled, the imped-
ance of
CE
OUT is equivalent to 75Ω in series with the
source driving
CE
IN. In the disabled mode, the 75Ω
transmission gate is off and an active pull-up connects
from
CE
OUT to V
CC
. This source turns off when the
transmission gate is enabled.
Applications Information
Connect a 0.1µF ceramic capacitor from V
CC
to GND,
as close to the device pins as possible. This reduces
the probability of resets due to high-frequency power-
supply transients. In a high-noise environment, addi-
tional bypass capacitance from V
CC
to ground may be
required. If long leads connect to the chip inputs,
ensure that these lines are free from ringing, etc., which
would forward bias the chip’s protection diodes.
