Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 28 February 2017
15 / 23
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
R
L
S1
C
L
open
G
Test data is given in Table 9.
Definitions for test circuit:
C
L
= load capacitance including jig and probe capacitance.
R
L
= load resistance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
S1 = test selection switch.
Figure 14. Test circuit for measuring switching times
Table 9. Test data
Input Load S1 positionType
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
74HC595-Q100 V
CC
6 ns 50 pF 1 kΩ open GND V
CC
74HCT595-Q100 3 V 6 ns 50 pF 1 kΩ open GND V
CC
