LTC2912ITS8-2#TRPBF

LTC2912
7
2912fb
For more information www.linear.com/LTC2912
BLOCK DIAGRAM
0.5V
+
3
VL
2
+
VH
+
UVLO
UVLO
2V
V
CC
+
1V
V
CC
OV PULSE
GENERATOR
DISABLE
DISABLE
OV LATCH
CLEAR/BYPASS
LTC2912-1, LTC2912-3
TMRV
CC
4
OV/OV
6
LATCH
8
+
1V
2µA
DIS
8
GND
2912 BD
5
1
UV PULSE
GENERATOR
OSCILLATOR
V
CC
400k
UV
7
400k
LTC2912-1
LTC2912-2
LTC2912-3
LTC2912-2
OV (Pin 6/Pin 3, LTC2912-3): Overvoltage Logic Output.
Asserts high with a weak internal pull‑up to V
CC
when the
VL input is above threshold. Latches high. May be pulled
above V
CC
using an external pull‑up. Leave pin open if
unused.
TMR (Pin 4/Pin 5): Reset Delay Timer. Attach an external
capacitor (C
TMR
) of at least 10pF to GND to set a reset
delay time of 9ms/nF. A 1nF capacitor will generate an
8.5ms reset delay time. Tie pin to V
CC
to bypass timer.
UV (Pin 7/Pin 2): Undervoltage Logic Output. Asserts low
when the VH input voltage is below threshold. Held low
for a programmed delay time after the VH input is valid.
Pin has a weak pull‑up to V
CC
and may be pulled above
V
CC
using an external pull‑up. Leave pin open if unused.
V
CC
(Pin 1/Pin 8): Supply Voltage. Bypass this pin to
GND with a 0.1µF (or greater) capacitor. Operates as a
direct supply input for voltages up to 6V. Operates as a
shunt regulator for supply voltages greater than 6V and
should have a resistance between the pin and the supply
to limit input current to no greater than
10mA. When
used
without a current‑limiting resistance, pin voltage must
not exceed 6V.
VH (Pin 2/Pin 7): Voltage High Input. When the voltage
on this pin is below 0.5V, an undervoltage condition is
triggered. Tie pin to V
CC
if unused.
VL (Pin 3/Pin 6): Voltage Low Input. When the voltage
on this pin is above 0.5V, an overvoltage condition is
triggered. Tie pin to GND if unused.
PIN FUNCTIONS
(DFN/TSOT Packages)
LTC2912
8
2912fb
For more information www.linear.com/LTC2912
APPLICATIONS INFORMATION
Voltage Monitoring
The LTC2912 is a low power voltage monitoring circuit
with an undervoltage and an overvoltage input. A timeout
period that holds OV and UV asserted after a fault has
cleared is adjustable using an external capacitor and may
be externally disabled. When configured to monitor a posi
tive voltage V
n
using the 3‑resistor circuit configuration
shown in Figure 1, VH will be connected to the high side
tap of the resistive divider and VL will be connected to the
low side tap of the resistive divider.
3-Step Design Procedure
The following 3‑step design procedure allows selecting
appropriate resistances to obtain the desired UV and OV
trip points for the voltage monitor circuit in Figure 1.
For supply monitoring, V
n
is the desired nominal operat‑
ing voltage, I
n
is the desired nominal current through the
resistive divider, V
OV
is the desired overvoltage trip point
and V
UV
is the desired undervoltage trip point.
1. Choose R
A
to obtain the desired OV trip point
R
A
is chosen to set the desired trip point for the over
voltage monitor.
R
A
=
0.5V
I
n
V
n
V
OV
(1)
2. Choose R
B
to obtain the desired UV trip point
Once R
A
is known, R
B
is chosen to set the desired trip
point for the undervoltage monitor.
R
B
=
0.5V
I
n
V
n
V
UV
R
A
(2)
3. Choose R
C
to complete the design
Once R
A
and R
B
are known, R
C
is determined by:
R
C
=
V
n
I
n
R
A
R
B
(3)
If any of the variables V
n
, I
n
, V
UV
or V
OV
change, then each
step must be recalculated.
Voltage Monitor Example
A typical voltage monitor application is shown in Figure 2.
The monitored voltage is a 5V ±10% supply. Nominal
current in the resistive divider is 10µA.
1. Find R
A
to set the OV trip point of the monitor.
R
A
=
0.5V
10µA
5V
5.5V
45.3k
2. Find R
B
to set the UV trip point of the monitor.
R
B
=
0.5V
10µA
5V
4.5V
45.3k 10.2k
3. Determine R
C
to complete the design.
R
C
=
5V
10µA
45.3k 10.2k 442k
Figure 1. 3-Resistor Positive UV/OV Monitoring Configuration
Figure 2. Typical Supply Monitor
+
+
+
0.5V
LTC2912
UV
VH
R
C
R
B
R
A
2912 F01
V
n
VL
OV
VH1
R
C
442k
R
B
10.2k
R
A
45.3k
V
CC
GND
LTC2912-1
VL1
2912 F02
OV
UV
V
CC
5V
V1
5V ±10%
LTC2912
9
2912fb
For more information www.linear.com/LTC2912
APPLICATIONS INFORMATION
Power-Up/Power-Down
As soon as V
CC
reaches 1V during power up, the UV output
asserts low and the OV output weakly pulls to V
CC
.
The LTC2912 is guaranteed to assert UV low, OV high
(LTC2912‑1, LTC2912‑2) and OV low (LTC2912‑3) under
conditions of low V
CC
, down to V
CC
= 1V. Above V
CC
=
2V (2.1V maximum), the VH and VL inputs take control.
Once the VH input and V
CC
become valid an internal timer
is started. After an adjustable delay time, UV weakly pulls
high.
Threshold Accuracy
Reset threshold accuracy is important in a supplysensitive
system. Ideally, such a system resets only if supply voltages
fall outside the exact thresholds for a specified margin.
Both LTC2912 inputs have a relative threshold accuracy
of ±1.5% over the full operating temperature range.
For example, when the LTC2912 is programmed to moni
tor a 5
V input with a 10% tolerance, the desired UV trip
point is 4.5V. Because of the ±1.5% relative accuracy of
the LTC2912, the UV trip point can be anywhere between
4.433V and 4.567V which is 4.5V ±1.5%.
Likewise, the accuracy of the resistances chosen for R
A
,
R
B
and R
C
can affect the UV and OV trip points as well.
Using the example just given, if the resistances used to
set the UV trip point have 1% accuracy, the UV trip range
is between 4.354V and 4.650V. This is illustrated in the
following calculations.
The UV trip point is given as:
V
UV
= 0.5V 1+
R
C
R
A
+ R
B
The two extreme conditions, with a relative accuracy of
1.5% and resistance accuracy of 1%, result in:
V
UV(MIN)
= 0.5V • 0.985 1+
R
C
0.99
R
A
+ R
B
( )
1.01
and
V
UV(MAX)
= 0.5V • 1.015 1+
R
C
1.01
R
A
+ R
B
( )
0.99
For a desired trip point of 4.5V,
R
C
R
A
+ R
B
= 8
Therefore,
V
UV(MIN)
= 0.5V • 0.985 1+ 8
0.99
1.01
= 4.354V
and
V
UV(MAX)
= 0.5V • 1.015 1+ 8
1.01
0.99
= 4.650V
Glitch Immunity
In any supervisory application, noise riding on the moni‑
tored DC
voltage causes spurious resets. To
solve this
problem without adding hysteresis, which causes a new
error term in the trip voltage, the LTC2912 lowpass filters
the output of the first stage comparator at each input. This
filter integrates the output of the comparator before as
serting the
UV or OV logic. A transient at the input of the
comparator
of sufficient magnitude and duration triggers
the output logic. The Typical Performance Characteristics
show a graph of the Transient Duration vs Comparator
Overdrive.
UV/OV Timing
The LTC2912 has an adjustable timeout period (t
UOTO
) that
holds OV, OV or UV asserted after each fault has cleared.
This delay assures a minimum reset pulse width allowing
settling time for the monitored voltage after it has entered
the “valid” region of operation.

LTC2912ITS8-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits 1x UV/OV V Mon
Lifecycle:
New from this manufacturer.
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