844001AGLF Datasheet 844001AGLFT, 844001AGLF | P7-P9

844001 Data Sheet

APPLICATION INFORMATION

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The 844001 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2 below were determined using a 26.5625MHz, 18pF

parallel resonant crystal and were chosen to minimize the ppm

error. The optimum C1 and C2 values can be slightly adjusted

for different board layouts.

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply

pins are vulnerable to random noise. The 844001 pro-

vides separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

and V

DDA

should be

individually connected to the power supply plane through vias, and

bypass capacitors should be used for each pin. To achieve optimum

jitter performance, power supply isolation is required. Figure 1 illus-

trates how a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each V

DDA

pin.

FIGURE 1. POWER SUPPLY FILTERING

10Ω

DDA

10μF

.01μF

3.3V or 2.5V

.01μF

844001 Data Sheet

3.3V, 2.5V LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 4. In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

unused outputs.

2.5V or 3.3V

VDD

100 Ohm Differential Transmission Line

100

LVDS_Driv er

844001 Data Sheet

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the 844001.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 844001 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V

= 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)

MAX

= V

DD_MAX

* (I

DD_MAX

+ I

DDA_MAX

) = 3.465V * (115mA + 12mA) = 440mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ

must be used. Assuming a moderate

air ﬂ ow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.440W *90.5°C/W = 109.8°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air ﬂ ow, and the

type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θ

FOR 8-PIN TSSOP, FORCED CONVECTION

by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

844001AGLF

Mfr. #:

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Clock Generators & Support Products FC1/FC2 FemtoClock LVDS Synthesize

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844001AGLF

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