Frequency Divider (AUXDIV1/AUXDIV0)
AUXDIV[1:0] sets the divisor to divide down the AUX
input frequency; see Table 12.
Audio Enable (AU4/AU3/AU2/AU1)
1 = Enable audio effect to EL output.
0 = Disable audio effect to EL output.
When FR_AM = 0 the EL outputs can be enabled
and disabled independently according to AU[4:1].
When FR_AM = 1 then all AU[4:1] bits must be set to 1
(i.e. AU[4:1] = 1111) to enable the audio effect on the
EL outputs.
EL Peak Ramping Time and EL Peak
Voltage Register (0x06, 0x07, 0x08, 0x09)
EL Ramping Time (RT4_ _/RT3_ _/RT2_ _/RT1_ _)
RT_ _[2:0] sets the ramp time of each EL output; see
Table 14.
EL Peak-to-Peak Voltage (EL1_ _/EL2_ _/
EL3_ _/EL4_ _)
EL _ _[4:0] controls the peak-to-peak voltage of each
EL output. When EL _ _[4:0] = 00000, the EL output fol-
lows COM. When EL_ _[4:0] = 11111, the EL output
has a 150V peak with respect to COM. The EL output
voltage rises linearly with EL_ _[4:0].
I
2
C Interface
The MAX14521E features an I
2
C-compatible as a slave
device, 2-wire serial interface consisting of a serial data
line (SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication to the device at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. A master device writes data to the
MAX14521E by transmitting the proper slave address
followed by the register address and then the data
word. Each transmit sequence is framed by a START
(S) or REPEATED START (Sr) condition and a STOP (P)
condition. Each word transmitted to the MAX14521E is
8 bits long and is followed by an acknowledge clock
pulse. A master reading data from the MAX14521E
transmits data on SDA in sync with the master-generat-
ed SCL pulses. The master acknowledges receipt of
each byte of data. Each read sequence is framed by a
START or REPEATED START condition, a not acknowl-
edge, and a STOP condition. SDA operates as both an
input and an open-drain output. A pullup resistor, typi-
cally greater than 500Ω, is required on SCL if there are
multiple masters on the bus, or if the master in a single-
master system has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the MAX14521E
from high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
MAX14521E
Quad, High-Voltage EL Lamp Driver
with I
2
C Interface
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