Data Sheet ADG1636
Rev. B | Page 15 of 16
TERMINOLOGY
I
DD
The positive supply current.
I
SS
The negative supply current.
V
D
(V
S
)
The analog voltage on Terminal D and Terminal S.
R
ON
The ohmic resistance between Terminal D and Terminal S.
R
FLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range.
I
S
(Off)
The source leakage current with the switch off.
I
D
(Off)
The drain leakage current with the switch off.
I
D
, I
S
(On)
The channel leakage current with the switch on.
V
INL
The maximum input voltage for Logic 0.
V
INH
The minimum input voltage for Logic 1.
I
INL
(I
INH
)
The input current of the digital input.
C
S
(Off)
The off switch source capacitance, which is measured with
reference to ground.
C
D
(Off)
The off switch drain capacitance, which is measured with
reference to ground.
C
D
, C
S
(On)
The on switch capacitance, which is measured with reference to
ground.
C
IN
The digital input capacitance.
t
TRANSITION
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one address
state to another.
t
ON
(EN)
The delay between applying the digital control input and the
output switching on. See Figure 30.
t
OFF
(EN)
The delay between applying the digital control input and the
output switching off. See Figure 30.
Charge Injection
A measure of the glitch impulse transferred from the digital input
to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
The ratio of the amplitude of signal on the output to the amplitude
of the modulation. This is a measure of the ability of the device
to avoid coupling noise and spurious signals that appear on the
supply voltage pin to the output of the switch. The dc voltage on the
device is modulated by a sine wave of 0.62 V p-p.
ADG1636 Data Sheet
Rev. B | Page 16 of 16
OUTLINE DIMENSIONS
16
9
81
PIN 1
SEATING
PLANE
0
°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
042709-A
1
0.65
BSC
BOTTOMVIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.50
0.40
0.30
SEATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
2.60
2.50 SQ
2.40
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-26)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
ADG1636BRUZ
−40°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
RU-16
ADG1636BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1636BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1636BCPZ-REEL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-26
ADG1636BCPZ-REEL7 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-26
1
Z = RoHS Compliant Part.
©20092016 Analog Devices, Inc. All rights reserved. Trademarks and
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D07983-0-3/16(B)

ADG1636BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs IC 1 Ohm 16V Dual SPDT CMOS
Lifecycle:
New from this manufacturer.
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