 |  |  | |
| PartNumber | SN74HC112DRG4 | SN74HC112DR | SN74HC112DR SOP3.9 |
| Description | Flip Flops Dual J K NEG Edge Triggered FlipFlop | Flip Flops Dual Neg-Edge-Trig J-K Flip-Flop | |
| Manufacturer | Texas Instruments | Texas Instruments | - |
| Product Category | Flip Flops | Logic - Flip Flops | - |
| RoHS | Y | - | - |
| Number of Circuits | 2 | 2 | - |
| Logic Family | HC | HC | - |
| Logic Type | CMOS | J-K Flip-Flop | - |
| Polarity | Inverting/Non-Inverting | Inverting/Non-Inverting | - |
| Input Type | CMOS, LVTTL | CMOS | - |
| Output Type | CMOS | Differential | - |
| Propagation Delay Time | 125 ns | 125 ns | - |
| High Level Output Current | - 4 mA | - 4 mA | - |
| Low Level Output Current | 4 mA | 4 mA | - |
| Supply Voltage Min | 2 V | - | - |
| Supply Voltage Max | 6 V | - | - |
| Minimum Operating Temperature | - 40 C | - 40 C | - |
| Maximum Operating Temperature | + 85 C | + 85 C | - |
| Mounting Style | SMD/SMT | SMD/SMT | - |
| Package / Case | SOP-16 | - | - |
| Packaging | Reel | Digi-ReelR Alternate Packaging | - |
| Function | JK Type | Set(Preset) and Reset | - |
| Height | 1.58 mm | - | - |
| Length | 9.9 mm | - | - |
| Operating Temperature Range | - 40 C to + 85 C | - | - |
| Quiescent Current | 4 uA | - | - |
| Series | SN74HC112 | 74HC | - |
| Width | 3.91 mm | - | - |
| Brand | Texas Instruments | - | - |
| Number of Channels | 2 | - | - |
| Number of Input Lines | 2 | 2 | - |
| Number of Output Lines | 1 | 3 | - |
| Operating Supply Voltage | 5 V | - | - |
| Product Type | Flip Flops | - | - |
| Reset Type | Set, Reset | - | - |
| Factory Pack Quantity | 2500 | - | - |
| Subcategory | Logic ICs | - | - |
| Unit Weight | 0.004998 oz | 0.004998 oz | - |
| Type | - | JK Type | - |
| Package Case | - | SOIC-16 | - |
| Operating Temperature | - | -40°C ~ 85°C (TA) | - |
| Mounting Type | - | Surface Mount | - |
| Voltage Supply | - | 2 V ~ 6 V | - |
| Frequency Clock | - | 60MHz | - |
| Number of Elements | - | 2 | - |
| Current Output High Low | - | 5.2mA, 5.2mA | - |
| Max Propagation Delay V Max CL | - | 21ns @ 6V, 50pF | - |
| Current Quiescent | - | 4μA | - |
| Number of Bits per Element | - | 1 | - |
| Trigger Type | - | Negative Edge | - |
| Input Capacitance | - | 3pF | - |
| Supply Voltage Max | - | 6 V | - |
| Supply Voltage Min | - | 2 V | - |
| Manufacturer | Part # | Description | RFQ |
|---|---|---|---|
Texas Instruments |
SN74HC112DRG4 | Flip Flops Dual J K NEG Edge Triggered FlipFlop | |
| SN74HC112DRG4 | Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SOIC T/R - Bulk (Alt: SN74HC112DRG4) | ||
| SN74HC112DR | Flip Flops Dual Neg-Edge-Trig J-K Flip-Flop | ||
| SN74HC112DR SOP3.9 | New and Original |