 |  | | |
| PartNumber | SN74LS107ANSR | SN74LS107ANS | SN74LS107ANSE4 |
| Description | Flip Flops Dual J-K Flip-Flops With Clear | J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14 | |
| Manufacturer | Texas Instruments | Texas Instruments | - |
| Product Category | Flip Flops | Logic - Flip Flops | - |
| RoHS | Y | - | - |
| Number of Circuits | 2 | 2 | - |
| Logic Family | LS | LS | - |
| Logic Type | J-K Type Flip-Flop | J-K Flip-Flop | - |
| Polarity | Inverting/Non-Inverting | Inverting/Non-Inverting | - |
| Input Type | TTL | TTL | - |
| Output Type | TTL | Differential | - |
| Propagation Delay Time | 20 ns | 20 ns | - |
| High Level Output Current | - 0.4 mA | - 0.4 mA | - |
| Low Level Output Current | 8 mA | 8 mA | - |
| Supply Voltage Min | 4.75 V | - | - |
| Supply Voltage Max | 5.25 V | - | - |
| Minimum Operating Temperature | 0 C | 0 C | - |
| Maximum Operating Temperature | + 70 C | + 70 C | - |
| Mounting Style | SMD/SMT | SMD/SMT | - |
| Package / Case | SO-14 | - | - |
| Packaging | Reel | Tape & Reel (TR) | - |
| Function | JK Type | Master Reset | - |
| Height | 1.95 mm | - | - |
| Length | 10.3 mm | - | - |
| Operating Temperature Range | 0 C to + 70 C | - | - |
| Series | SN74LS107A | 74LS | - |
| Width | 5.3 mm | - | - |
| Brand | Texas Instruments | - | - |
| Number of Channels | 2 | - | - |
| Number of Input Lines | 4 | 4 | - |
| Number of Output Lines | 2 | 2 | - |
| Operating Supply Voltage | 4.75 V to 5.25 V | - | - |
| Product Type | Flip Flops | - | - |
| Reset Type | Reset | - | - |
| Factory Pack Quantity | 2000 | - | - |
| Subcategory | Logic ICs | - | - |
| Unit Weight | 0.007348 oz | 0.007348 oz | - |
| Type | - | JK Type | - |
| Package Case | - | SOP-14 | - |
| Operating Temperature | - | 0°C ~ 70°C (TA) | - |
| Mounting Type | - | Surface Mount | - |
| Voltage Supply | - | 4.75 V ~ 5.25 V | - |
| Frequency Clock | - | 45MHz | - |
| Number of Elements | - | 2 | - |
| Current Output High Low | - | 400μA, 8mA | - |
| Max Propagation Delay V Max CL | - | 20ns @ 5V, 15pF | - |
| Current Quiescent | - | 6mA | - |
| Number of Bits per Element | - | 1 | - |
| Trigger Type | - | Negative Edge | - |
| Input Capacitance | - | - | - |
| Supply Voltage Max | - | 5.25 V | - |
| Supply Voltage Min | - | 4.75 V | - |
| Manufacturer | Part # | Description | RFQ |
|---|---|---|---|
Texas Instruments |
SN74LS107ANSR | Flip Flops Dual J-K Flip-Flops With Clear | |
| SN74LS107ANSR | Flip Flops Dual J-K Flip-Flops With Clea | ||
| SN74LS107ANS | J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14 | ||
| SN74LS107ANSE4 | New and Original | ||
| SN74LS107ANSRG4 | Flip Flops Dual J to K FlipFlop |