| |  |  | |
| PartNumber | ispPAC-CLK5320S-01TN64C | ISPPAC-CLK5320S-01T64I | ISPPAC-CLK5320S-01T64C |
| Description | Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End | IC BUFFER FANOUT ISP UNIV 64TQFP | IC BUFFER FANOUT ISP UNIV 64TQFP |
| Manufacturer | Lattice | Lattice Semiconductor Corporation | Lattice Semiconductor Corporation |
| Product Category | Clock Drivers & Distribution | Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers | Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers |
| RoHS | Y | - | - |
| Series | ispPAC-CLK5320S | ispClock | ispClock |
| Multiply / Divide Factor | 2:20 | - | - |
| Output Type | EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL | - | - |
| Max Output Freq | 267 MHz | - | - |
| Supply Voltage Max | 3.6 V | - | - |
| Supply Voltage Min | 3 V | - | - |
| Minimum Operating Temperature | 0 C | - | - |
| Maximum Operating Temperature | + 70 C | - | - |
| Mounting Style | SMD/SMT | - | - |
| Package / Case | TQFP-64 | - | - |
| Packaging | Tray | Tray | Tray |
| Height | 1.4 mm | - | - |
| Input Type | HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL | - | - |
| Length | 10 mm | - | - |
| Type | Zero Delay Programmable PLL Clock Generator | Clock Generator, Fanout Distribution, Zero Delay Buffer | Clock Generator, Fanout Distribution, Zero Delay Buffer |
| Width | 10 mm | - | - |
| Brand | Lattice | - | - |
| Maximum Input Frequency | 267 MHz | - | - |
| Moisture Sensitive | Yes | - | - |
| Operating Supply Current | 1.5 mA | - | - |
| Pd Power Dissipation | 888 mW | - | - |
| Product Type | Clock Drivers & Distribution | - | - |
| Factory Pack Quantity | 160 | - | - |
| Subcategory | Clock & Timer ICs | - | - |
| Tradename | ispClock | - | - |
| Unit Weight | 0.012720 oz | - | - |
| Package Case | - | 64-LQFP | 64-LQFP |
| Operating Temperature | - | -40°C ~ 85°C | 0°C ~ 70°C |
| Mounting Type | - | Surface Mount | Surface Mount |
| Voltage Supply | - | 3 V ~ 3.6 V | 3 V ~ 3.6 V |
| Supplier Device Package | - | 64-TQFP (10x10) | 64-TQFP (10x10) |
| PLL | - | Yes with Bypass | Yes with Bypass |
| Input | - | HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL | HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL |
| Output | - | eHSTL, HSTL, LVCMOS, LVTTL, SSTL | eHSTL, HSTL, LVCMOS, LVTTL, SSTL |
| Number of Circuits | - | 1 | 1 |
| Ratio InputOutput | - | 1899/12/30 2:20:00 | 1899/12/30 2:20:00 |
| Differential InputOutput | - | Yes/No | Yes/No |
| Frequency Max | - | 267MHz | 267MHz |
| Divider Multiplier | - | Yes/No | Yes/No |
