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| PartNumber | ispPAC-CLK5620AV-01TN100C | ISPPAC-CLK5620AV-01T100C | ISPPAC-CLK5620AV-01T100I |
| Description | Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I | IC CLK GENERATOR ISP ZD 100-TQFP | Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I |
| Manufacturer | Lattice | Lattice Semiconductor Corporation | Lattice Semiconductor Corporation |
| Product Category | Clock Drivers & Distribution | Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers | Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers |
| RoHS | Y | - | - |
| Series | ispPAC-CLK5620AV | ispClock | ispClock |
| Multiply / Divide Factor | 2:20 | - | - |
| Output Type | EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL | - | - |
| Max Output Freq | 400 MHz | - | - |
| Supply Voltage Max | 3.6 V | - | - |
| Supply Voltage Min | 3 V | - | - |
| Minimum Operating Temperature | 0 C | - | - |
| Maximum Operating Temperature | + 70 C | - | - |
| Mounting Style | SMD/SMT | - | - |
| Package / Case | TQFP-100 | - | - |
| Packaging | Tray | Tray | Tray |
| Height | 1.4 mm | - | - |
| Input Type | HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL | - | - |
| Length | 14 mm | - | - |
| Number of Outputs | 20 | - | - |
| Type | Zero Delay Programmable PLL Clock Generator | * | * |
| Width | 14 mm | - | - |
| Brand | Lattice | - | - |
| Maximum Input Frequency | 400 MHz | - | - |
| Moisture Sensitive | Yes | - | - |
| Operating Supply Current | 130 mA | - | - |
| Pd Power Dissipation | 1.75 W | - | - |
| Product Type | Clock Drivers & Distribution | - | - |
| Factory Pack Quantity | 90 | - | - |
| Subcategory | Clock & Timer ICs | - | - |
| Tradename | ispClock | - | - |
| Unit Weight | 0.023175 oz | - | - |
| Package Case | - | 100-LQFP | 100-LQFP |
| Operating Temperature | - | 0°C ~ 70°C | -40°C ~ 85°C |
| Mounting Type | - | Surface Mount | Surface Mount |
| Voltage Supply | - | 3 V ~ 3.6 V | 3 V ~ 3.6 V |
| Supplier Device Package | - | 100-TQFP (14x14) | 100-TQFP (14x14) |
| PLL | - | Yes with Bypass | Yes with Bypass |
| Input | - | HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL | HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL |
| Output | - | EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL | EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL |
| Number of Circuits | - | 1 | 1 |
| Ratio InputOutput | - | 1899/12/30 2:20:00 | 1899/12/30 2:20:00 |
| Differential InputOutput | - | Yes/Yes | Yes/Yes |
| Frequency Max | - | 400MHz | 400MHz |
| Divider Multiplier | - | Yes/No | Yes/No |
