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CAT28C256H1315

P1-P3P4-P6P7-P9P10-P12P13-P14
CAT28C256
http://onsemi.com
4
Table 4. MODE SELECTION
Mode CE WE OE I/O Power
Read L H L D
OUT
ACTIVE
Byte Write (WE Controlled) L H D
IN
ACTIVE
Byte Write (CE Controlled) L H D
IN
ACTIVE
Standby and Write Inhibit H X X High−Z STANDBY
Read and Write Inhibit X H H High−Z ACTIVE
Table 5. CAPACITANCE (T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol Test Max Conditions Units
C
I/O
(Note 7) Input/Output Capacitance 10 V
I/O
= 0 V pF
C
IN
(Note 7) Input Capacitance 6 V
IN
= 0 V pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
Table 6. A.C. CHARACTERISTICS, READ CYCLE (V
CC
= 5 V ±10%, unless otherwise specified.)
Symbol Parameter
28C256−12 28C256−15
Units
Min Max Min Max
t
RC
Read Cycle Time 120 150 ns
t
CE
CE Access Time 120 150 ns
t
AA
Address Access Time 120 150 ns
t
OE
OE Access Time 50 70 ns
t
LZ
(Note 8) CE Low to Active Output 0 0 ns
t
OLZ
(Note 8) OE Low to Active Output 0 0 ns
t
HZ
(Notes 8, 9) CE High to High−Z Output 50 50 ns
t
OHZ
(Notes 8, 9) OE High to High−Z Output 50 50 ns
t
OH
(Note 8) Output Hold from Address Change 0 0 ns
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
CAT28C256
http://onsemi.com
5
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V
CC
= 5 V ±10%, unless otherwise specified.)
Symbol Parameter
28C256−12 28C256−15
Units
Min Max Min Max
t
WC
Write Cycle Time 5 5 ms
t
AS
Address Setup Time 0 0 ns
t
AH
Address Hold Time 50 50 ns
t
CS
CE Setup Time 0 0 ns
t
CH
CE Hold Time 0 0 ns
t
CW
(Note 10) CE Pulse Time 100 100 ns
t
OES
OE Setup Time 0 0 ns
t
OEH
OE Hold Time 0 0 ns
t
WP
(Note 10) WE Pulse Width 100 100 ns
t
DS
Data Setup Time 50 50 ns
t
DH
Data Hold Time 10 10 ns
t
INIT
(Note 11) Write Inhibit Period After Power−up 5 10 5 10 ms
t
BLC
(Notes 11, 12) Byte Load Cycle Time 0.1 100 0.1 100
ms
10.A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within t
BLC
max. stops the timer.
Figure 2. A.C. Testing Input/Output Waveform (Note 13)
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.8 V
0.0 V
V
CC
− 0.3 V
13.Input rise and fall times (10% and 90%) < 10 ns.
Figure 3. A.C. Testing Load Circuit (example)
1.3 V
DEVICE
UNDER
TEST
1N914
3.3 K
OUT
C
L
= 100 pF
C
L
INCLUDES JIG CAPACITANCE
CAT28C256
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6
DEVICE OPERATION
Read
Data stored in the CAT28C256 is transferred to the data
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2−line control architecture can be used
to eliminate bus contention in a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
Figure 4. Read Cycle
ADDRESS
DATA OUT DATA VALIDDATA VALID
HIGH−Z
t
OHZ
t
HZ
t
AA
t
OH
t
OE
t
OLZ
t
CE
t
LZ
t
RC
V
IH
CE
OE
WE
Figure 5. Byte Write Cycle [WE Controlled]
ADDRESS
DATA OUT
DATA IN
DATA VALID
HIGH−Z
WE
OE
CE
t
AH
t
AS
t
CS
t
CH
t
WP
t
OES
t
OEH
t
BLC
t
DS
t
DH
t
WC
P1-P3P4-P6P7-P9P10-P12P13-P14

CAT28C256H1315

Mfr. #:
Buy CAT28C256H1315
Manufacturer:
ON Semiconductor
Description:
EEPROM (32kx8) 256K 5V 150
Lifecycle:
New from this manufacturer.
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