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74F646SPC

P1-P3P4-P6
© 2004 Fairchild Semiconductor Corporation DS009580 www.fairchildsemi.com
March 1988
Revised January 2004
74F646 Octal Transceiver/Register with 3-STATE Outputs
74F646
Octal Transceiver/Register with 3-STATE Outputs
General Description
These devices consist of bus transceiver circuits with
3-STATE, D-type flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from the input
bus or from the internal registers. Data on the A or B bus
will be clocked into the registers as the appropriate clock
pin goes to a high logic level. Control G
and direction pins
are provided to control the transceiver function. In the
transceiver mode, data present at the high impedance port
may be stored in either the A or the B register or in both.
The select controls can multiplex stored and real-time
(transparent mode) data. The direction control determines
which bus will receive data when the enable control G
is
Active LOW. In the isolation mode (control G
HIGH), A data
may be stored in the B register and/or B data may be
stored in the A register.
Features
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ 74F646 has non-inverting data paths
■ 3-STATE outputs
■ 300 mil slim DIP
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74F646MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74F646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com 2
74F646
Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant = LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G
and DIR Inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
A
0
–A
7
Data Register A Inputs/ 3.5/1.083 70 µA/−650 µA
3-STATE Outputs 600/106.6 (80)
−12 mA/64 mA (48 mA)
B
0
–B
7
Data Register B Inputs/ 3.5/1.083 70 µA/−650 µA
3-STATE Outputs 600/106.6 (80)
−12 mA/64 mA (48 mA)
CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20
µA/−0.6 mA
SAB, SBA Select Inputs 1.0/1.0 20
µA/−0.6 mA
G
Output Enable Input 1.0/1.0 20 µA/−0.6 mA
DIR Direction Control Input 1.0/1.0 20
µA/−0.6 mA
Inputs Data I/O (Note 1)
Function
G
DIR CPAB CPBA SAB SBA
A
0
–A
7
B
0
–B
7
H X H or L H or L X X Isolation
HX
X X X Input Input Clock A
n
Data into A Register
HXX
X X Clock B
n
Data into B Register
LHXXLX A
n
to B
n
—Real Time (Transparent Mode)
LH
X L X Input Output Clock A
n
Data into A Register
L H H or L X H X A Register to B
n
(Stored Mode)
LH
X H X Clock A
n
Data into A Register and Output to B
n
LLXXXL B
n
to A
n
—Real Time (Transparent Mode)
LLX
X L Output Input Clock B
n
Data into B Register
L L X H or L X H B Register to A
n
(Stored Mode)
LLX
X H Clock B
n
Data into B Register and Output to A
n
3 www.fairchildsemi.com
74F646
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Junction Temperature under Bias
−55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 3)
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output
−0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambient Temperature 0
°C to +70°C
Supply Voltage
+4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min I
IN
= −18 mA (Non I/O Pins)
V
OH
Output HIGH 10% V
CC
2.0 V Min I
OH
= −15 mA (A
n
, B
n
)
Voltage
V
OL
Output LOW 10% V
CC
0.55 V Min I
OL
= 64 mA (A
n
, B
n
)
Voltage
I
IH
Input HIGH
5.0 µAMaxV
IN
= 2.7V (Non I/O Pins)
Current
I
BVI
Input HIGH Current
7.0 µAMaxV
IN
= 7.0V (Non I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current
0.5 mA Max V
IN
= 5.5V (A
n
, B
n
)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max V
IN
= 0.5V (Non I/O Pins)
I
IH
+ I
OZH
Output Leakage Current 70 µAMaxV
OUT
= 2.7V (A
n
, B
n
)
I
IL
+ I
OZL
Output Leakage Current −650 µAMaxV
OUT
= 0.5V (A
n
, B
n
)
I
OS
Output Short-Circuit Current −100 −225 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCH
Power Supply Current 135 mA Max V
O
= HIGH
I
CCL
Power Supply Current 150 mA Max V
O
= LOW
I
CCZ
Power Supply Current 150 mA Max V
O
= HIGH Z
P1-P3P4-P6

74F646SPC

Mfr. #:
Buy 74F646SPC
Manufacturer:
ON Semiconductor
Description:
IC TXRX NON-INVERT 5.5V 24DIP
Lifecycle:
New from this manufacturer.
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