NCP1000, NCP1001, NCP1002
http://onsemi.com
9
Current Limit Comparator and Power Switch Circuit
The NCP1000 series uses cycle--by--cyclecurrent limiting
as a means of protecting the output switch transistor from
overstress. Current limiting is implemented by monitoring
the instantaneous output switch current during conduction,
and upon sensing an overcurrent condition, immediately
turning off the switch for the duration of the Oscillator
ramp--down period.
The Power Switch Circuit is constructed using a
SENSEFETt allowing a virtually lossless method of
monitoring the drain current. A small number of the power
MOSFET cells are used for current sensing by connecting
their individual sources to a single ground referenced sense
resistor , R
pk
. The current limit comparator detects if the
voltage across R
pk
exceeds the reference level that is present
at the noninverting input. If exceeded, the comparator
quickly resets the PWM Latch, thus protecting the Power
Switch Circuit. Figure 9 shows that this detection method
yields a relatively constant current limit threshold over
temperature. The high voltage Power Switch Circuit is
integrated with the control logic circuitry and is designed to
directly drive the converter transformer. The Power Switch
Circuit is capable of switching 700 V with an associated
drain current that ranges from 0.5 A to 1.5 A. Proper drain
voltage snubbing during converter startup and overload is
mandatory for reliable device operation.
A Leading Edge Blanking circuit was placed in the current
sensing signal path to prevent a premature reset of the PWM
Latch. A potential premature reset signal is generated each
time the Power Switch Circuit is driven into conduction and
appears as a narrow voltage spike across current sense
resistor R
pk
. The spike is due to the MOSFET gate to source
capacitance, transformer interwinding capacitance, and
output rectifier recovery time. The Leading Edge Blanking
circuit has a dynamic behavior that masks the current signal
until the Power Switch Circuit turn--on transition is
completed.
The current limit propagation delay time is typically
220 ns. This time is measured from when an overcurrent
appears at the Power Switch Circuit drain, to the beginning
of turn--off. Care must be taken during transformer
saturation so that the maximum device current limit rating
is not exceeded. To determine the peak Power Switch Circuit
current at turn off, the effect of the propagation delay must
be taken into account. To do this, use the appropriate Current
Limit Threshold value from the electrical tables, and then
add the ΔIpk based on the di/dt from Figure 16. The di/dt of
the circuit can be calculated by the following formula:
di∕dt (A∕ms) = V∕L
where:
V is the rectified, filtered input voltage (volts)
L is the primary inductance of the flyback transformer
(Henries)
High Voltage Startup
The NCP1000--1002 contain an internal startup circuit
that eliminates the need for external startup components. In
addition, this circuit increases the efficiency of the supply as
it uses no power when in the normal mode of operation, but
instead uses the power supplied by the auxiliary winding.
Rectified, filtered ac line voltage is connected to pin 4. An
internal JFET allows current to flow from the startup pin, to
the V
CC
pin at a current of approximately 3.0 mA. Figure 5
shows the startup current out of pin 1 which charges the
capacitor(s) connected to this pin.
The start circuit will be enhanced (conducting) when the
voltage at Pin 1 (V
CC
) is less than 7.5 V. It will remain
enhanced until the V
CC
voltage reaches 8.5 V. At this point
the Power Switch Circuit will be disabled, and the unit will
generate voltage via the auxiliary winding to maintain
proper operation of the device. Figure 4 shows the charge
time for turn--on vs. V
CC
capacitance when the unit is
initially energized.
If the V
CC
voltage drops below 7.5 V (e.g. current limit
mode), the start circuit will again begin conducting, and will
charge up the V
CC
cap until the 8.5 V limit is reached.
V
CC
Limiter and Undervoltage Lockout
The undervoltage lockout (UVLO) is designed to
guarantee that the integrated circuit has sufficient voltage to
be fully functional before the output stage is enabled. It
inhibits operation of the major functions of the device by
disabling the Internal Bias circuitry, and assures that the
Power Switch Circuit remains in its “off’’ state as the bias
voltage is initially brought up from zero volts. When the
NCP100x is in the “off’’ state, the High Voltage Startup
circuit is operational. The UVLO is a hysteretic switch and
will hold the device in its “off’’ state any time that the V
CC
voltage is less than 7.5 V. As the V
CC
increases past 7.5 V,
the NCP100x will remain off until the upper threshold of 8.6
V is reached. At this time the power converter is enabled and
will commence operation. The UVLO will allow the unit to
continue to operate as long as the V
CC
voltage exceeds 7.5 V.
The temperature characteristics of the UVLO circuit are
shown in Figure 8.
If the converter output is overloaded or shorted, the device
will enter the auto restart mode. This happens when the
auxiliary winding of the power transformer does not have
sufficient voltage to support the V
CC
requirements of the
chip. Once the chip is operational, if the V
CC
voltage falls
below 7.5 V the unit will shut down, and the High Voltage
Startup circuit will be enabled. This will charge the V
CC
cap
up to 8.5 V, which will clock the divide by eight counter. The
divide by eight counter holds the Power Switch Circuit off.
This causes the V
CC
cap to discharge. It will continue to
discharge and recharge for eight consecutive cycles. After
the eighth cycle, the unit will turn on again. If the fault
remains, the unit will again cycle through the auto restart
mode; if the fault has cleared the unit will begin normal
operation. The auto restart mode greatly reduces the power
dissipation of the power devices in the circuit and improves
