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LT6660HCDC-5#TRPBF

P1-P3P4-P6P7-P9P10-P12
LT6660
10
6660fa
Output Accuracy
Like all references, either series or shunt, the error budget
of the LT6660s is made up of primarily three components:
initial accuracy, temperature coefficient and load regulation.
Line regulation is neglected because it typically contributes
only 150ppm/V. The LT6660s typically shift 0.02% when
soldered into a PCB, so this is also neglected. The output
errors are calculated as follows for a 100µA load and 0°C
to 70°C temperature range:
LT6660HCDC
Initial Accuracy = 0.2%
For I
OUT
= 100µA
ΔV
OUT
= (4000ppm/mA)(0.1mA) = 0.04%
For Temperature 0°C to 70°C the maximum ΔT = 70°C
ΔV
OUT
= (20ppm/°C)(70°C) = 0.14%
Total worst-case output error is:
0.2% + 0.04% + 0.14% = 0.380%
Table 2 gives the worst-case accuracy for LT6660HC,
LT6660JC and LT6660KC from 0°C to 70°C, and shows
that if the LT6660HC is used as a reference instead of a
regulator, it is capable of 8 bits of absolute accuracy over
temperature without a system calibration.
Table 2. Worst-Case Output Accuracy over Temperature
I
OUT
LT6660HCDC LT6660JCDC LT6660KCDC
0µA 0.340% 0.540% 0.850%
100µA 0.380% 0.580% 0.890%
10mA 0.640% 0.840% 1.15%
20mA 0.540% 0.740% 1.05%
APPLICATIO S I FOR ATIO
W UU
U
LT6660
11
6660fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
2.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (W-TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
BOTTOM VIEW—EXPOSED PAD
1.00 ± 0.05
(2 SIDES)
1.35 ± 0.05
(2 SIDES)
0.75 ±0.05
0.40 ±0.05
0.70 ±0.05
1
3
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC3) DFN 1205 REV Ø
0.25 ± 0.05
R = 0.05
TYP
R = 0.115 TYP
0.50 BSC
0.25 ± 0.05
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.00 ±0.05
(2 SIDES)
1.30 ±0.05
2.00 ±0.05
PACKAGE
OUTLINE
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
DC Package
3-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1717 Rev Ø)
LT6660
12
6660fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2006
LT 0406 REV A PRINTED IN USA
V
+
≥ (V
OUT
+ 1.8V)
LT6660
OUT
GND
IN
6660 TA03
2N2905
V
OUT
100mA
47µF
2µF
SOLID
TANT
R1
220Ω
+
+
3
2
1
6660 TA04
2N2905
V
OUT
100mA
2µF
SOLID
TANT
D1*
LED
V
+
≥ V
OUT
+ 2.8V
8.2Ω
R1
220Ω
GLOWS IN CURRENT LIMIT,
DO NOT OMIT
*
47µF
+
+
LT6660
OUT
GND
IN
3
2
1
6660 TA02
R
L
40mA
V
+
R1*
V
OUT
TYPICAL LOAD
CURRENT = 50mA
SELECT R1 TO DELIVER 80% OF TYPICAL LOAD CURRENT.
LT6660 WILL THEN SOURCE AS NECESSARY TO MAINTAIN
PROPER OUTPUT. DO NOT REMOVE LOAD AS OUTPUT WILL
BE DRIVEN UNREGULATED HIGH. LINE REGULATION IS
DEGRADED IN THIS APPLICATION
*
10mA
47µF
+
LT6660
OUT
GND
IN
R1 =
V
+
– V
OUT
40mA
3
2
1
TYPICAL APPLICATIO
U
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P1-P3P4-P6P7-P9P10-P12

LT6660HCDC-5#TRPBF

Mfr. #:
Buy LT6660HCDC-5#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Voltage References 5V Low Cost uP Prec Series Ref.
Lifecycle:
New from this manufacturer.
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