74ALVC32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 20 January 2014 3 of 14
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level
L = LOW voltage level
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When V
CC
= 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
Table 2. Pin description
Symbol Pin Description
nA 1, 4, 9, 12 data input
nB 2, 5, 10, 13 data input
nY 3, 6, 8, 11 data output
V
CC
14 supply voltage
GND 7 ground (0 V)
Table 3. Function table
[1]
Input nA Input nB Output nY
LLL
LHH
HLH
HHH
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +4.6 V
I
IK
input clamping current V
I
<0V 50 - mA
V
I
input voltage 0.5 +4.6 V
I
OK
output clamping current V
O
>V
CC
or V
O
<0V - 50 mA
V
O
output voltage output HIGH or LOW state
[1]
[2]
0.5 V
CC
+0.5 V
output 3-state 0.5 +4.6 V
power-down mode, V
CC
= 0 V
[2]
0.5 +4.6 V
I
O
output current V
O
=0V toV
CC
- 50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +85 C
[3]
-500 mW