74ALVC32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 20 January 2014 7 of 14
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 7. Test circuitry for measuring switching times
9
0
9
0
W
:
W
:
9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0
W
I
W
U
W
U
W
I
DDH
9
(;7
9
&&
9
,
9
2
'87
&
/
5
7
5
/
5
/
*
Table 9. Test data
Supply voltage V
CC
Input Load V
EXT
V
I
t
r
, t
f
C
L
R
L
t
PLH
, t
PHL
t
PLZ
, t
PZL
t
PHZ
, t
PZH
1.65 V to 1.95 V V
CC
2.0 ns 30 pF 1 k open 2 V
CC
GND
2.3 V to 2.7 V V
CC
2.0 ns 30 pF 500 open 2 V
CC
GND
2.7V 2.7V 2.5 ns 50 pF 500 open 6 V GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 6 V GND
