LT5571
10
5571f
Table 1. Typical Performance Characteristics vs V
CM
for f
LO
= 900MHz, P
LO
= 0dBm
V
CM
(V) I
CC
(mA) G
V
(dB) OP1dB (dBm) OIP2 (dBm) OIP3 (dBm) NFloor (dBm/Hz) LOFT (dBm) IR (dBc)
0.1 55.3 –4.5 –1.5 53.4 9.2 –163.6 –53.6 37.0
0.2 65.3 –3.9 2.0 51.7 11.2 –161.8 –50.3 40.4
0.25 70.3 –3.7 3.4 51.9 13.3 –161.2 –49.0 43.5
0.3 75.7 –3.6 4.5 52.1 15.6 –160.5 –47.7 43.9
0.4 86.4 –3.5 6.3 53.1 18.7 –159.6 –45.3 45.1
0.5 97.1 –3.6 7.9 53.0 20.6 –158.7 –43.1 45.4
0.6 108.1 –3.7 8.4 53.7 22.1 –157.9 –41.2 45.6
APPLICATIONS INFORMATION
full 0V to 1V swing on each baseband input (2V
P-P,DIFF
).
This maximum RF output level is limited by the 0.5V
PEAK
maximum baseband swing possible for a 0.5V
DC
com-
mon-mode voltage level (assuming no negative supply
bias voltage is available).
It is possible to bias the LT5571 to a common mode
voltage level other than 0.5V. Table 1 shows the typical
performance for different common mode voltages.
LO Section
The internal LO input amplifi er performs single-ended to
differential conversion of the LO input signal. Figure 4
shows the equivalent circuit schematic of the LO input.
The internal differential LO signal is split into in-phase and
quadrature (90° phase shifted) signals to drive LO buffer
sections. These buffers drive the double balanced I and
Q mixers. The phase relationship between the LO input
and the internal in-phase LO and quadrature LO signals
is fi xed, and is independent of start-up conditions. The
phase shifters are designed to deliver accurate quadrature
signals for an LO frequency near 900MHz. For frequen-
cies signifi cantly below 750MHz or above 1100MHz, the
quadrature accuracy will diminish, causing the image
rejection to degrade. The LO pin input impedance is about
50Ω, and the recommended LO input power window is
–2dBm to 2dBm. For P
LO
< –2dBm input power, the gain,
OIP2, OIP3, dynamic-range (in dBc/Hz) and image rejection
will degrade, especially at T
A
= 85°C.
Harmonics present on the LO signal can degrade the image
rejection, because they introduce a small excess phase shift
in the internal phase splitter. For the second (at 1.8GHz)
and third harmonics (at 2.7GHz) at –20dBc level, the in-
troduced signal at the image frequency is about –61dBc
or lower, corresponding to an excess phase shift much
less than 1 degree. For the second and third harmonics at
–10dBc, still the introduced signal at the image frequency
is about –51dBc. Higher harmonics than the third will have
less impact. The LO return loss typically will be better than
11dB over the 750MHz to 1GHz range. Table 2 shows the
LO port input impedance vs frequency.
Table 2. LO Port Input Impedance vs Frequency for EN = High
and P
LO
= 0dBm
FREQUENCY INPUT IMPEDANCE
S
11
(MHz) (Ω)
Mag Angle
500 47.2 + j11.7 0.123 97
600 58.4 + j8.3 0.108 40
700 65.0 – j0.6 0.131 –2
800 66.1 – j12.2 0.173 –31
900 60.7 – j22.5 0.221 –53
1000 53.3 – j25.1 0.239 –69
1100 48.4 – j25.1 0.248 –79
1200 42.7 – j26.4 0.285 –89
The return loss S
11
on the LO port can be improved at
lower frequencies by adding a shunt capacitor. The input
impedance of the LO port is different if the part is in
shut-down mode. The LO input impedance for EN = Low
is given in Table 3.
Figure 4. Equivalent Circuit Schematic of the LO Input
V
CC
20pF
LO
INPUT
Z
IN
60
5571 F04
LT5571
11
5571f
APPLICATIONS INFORMATION
Table 3. LO Port Input Impedance vs Frequency for EN = Low
and P
LO
= 0dBm
FREQUENCY INPUT IMPEDANCE
S
11
(MHz) (Ω)
Mag Angle
500 35.6 + j42.1 0.467 83
600 65.5 + j70.1 0.531 46
700 163 + j76.3 0.602 14
800 188 – j95.2 0.654 –13
900 72.9 – j114 0.692 –36
1000 34.3 – j83.5 0.715 –56
1100 21.6 – j63.3 0.726 –73
1200 16.4 – j50.5 0.727 –86
RF Section
After up-conversion, the RF outputs of the I and Q mixers are
combined. An on-chip balun performs internal differential
to single-ended output conversion, while transforming the
output signal impedance to 50Ω. Table 4 shows the RF
port output impedance vs frequency.
Table 4. RF Port Output Impedance vs Frequency for EN = High
and P
LO
= 0dBm
FREQUENCY OUTPUT IMPEDANCE
S
22
(MHz) (Ω)
Mag Angle
500 22.2 + j5.2 0.390 165
600 28.4 + j11.7 0.311 143
700 38.8 + j14.3 0.202 119
800 49.4 + j6.8 0.068 91
900 49.4 – j5.8 0.058 –92
1000 42.7 – j11.7 0.149 –115
1100 36.9 – j12.6 0.207 –128
1200 33.2 – j11.3 0.241 –138
The RF output S
22
with no LO power applied is given in
Table 5.
Table 5. RF Port Output Impedance vs Frequency for EN = High
and No LO Power Applied
FREQUENCY OUTPUT IMPEDANCE
S
22
(MHz) (Ω)
Mag Angle
500 22.9 + j5.3 0.377 165
600 30.0 + j11.2 0.283 143
700 40.6 + j11.2 0.160 123
800 47.3 + j1.9 0.034 145
900 44.2 – j7.4 0.099 –123
1000 38.4 – j10.4 0.175 –131
1100 34.2 – j10.2 0.221 –140
1200 31.7 – j8.7 0.246 –148
For EN = Low the S
22
is given in Table 6.
Table 6. RF Port Output Impedance vs Frequency for EN = Low
FREQUENCY OUTPUT IMPEDANCE
S
22
(MHz) (Ω)
Mag Angle
500 21.5 + j5.0 0.403 166
600 26.9 + j11.8 0.333 144
700 36.5 + j16.0 0.239 120
800 48.8 + j11.2 0.113 89
900 52.8 – j2.2 0.035 –38
1000 46.6 – j11.5 0.123 –99
1100 39.7 – j13.9 0.191 –117
1200 35.0 – j13.0 0.232 –130
To improve S
22
for lower frequencies, a series capacitor
can be added to the RF output. At higher frequencies, a
shunt inductor can improve the S
22
. Figure 5 shows the
equivalent circuit schematic of the RF output.
Note that an ESD diode is connected internally from the
RF output to ground. For strong output RF signal levels
(higher than 3dBm) this ESD diode can degrade the lin-
earity performance if an external 50Ω termination imped-
ance is connected directly to ground. To prevent this, a
coupling capacitor can be inserted in the RF output line.
This is strongly recommended during 1dB compression
measurements.
21pF
V
CC
1pF47
RF
OUTPUT
7nH
5571 F05
Figure 5. Equivalent Circuit Schematic of the RF Output
Enable Interface
Figure 6 shows a simplifi ed schematic of the EN pin inter-
face. The voltage necessary to turn on the LT5571 is 1V.
To disable (shut down) the chip, the enable voltage must
be below 0.5V. If the EN pin is not connected, the chip is
disabled. This EN = Low condition is guaranteed by the
75kΩ on-chip pull-down resistor.
It is important that the voltage at the EN pin does not
exceed V
CC
by more than 0.5V. If this should occur, the
LT5571
12
5571f
APPLICATIONS INFORMATION
full chip supply current could be sourced through the EN
pin ESD protection diodes, which are not designed for this
purpose. Damage to the chip may result.
Evaluation Board
Figure 7 shows the evaluation board schematic. A good
ground connection is required for the LT5571’s Exposed
Pad. If this is not done properly, the RF performance will
degrade. Additionally, the Exposed Pad provides heat sink-
ing for the part and minimizes the possibility of the chip
EN
V
CC
75k
5571 F06
25k
Figure 6. EN Pin Interface
BBIPBBIM
J1
16 15
R5
49.9
R1
100
V
CC
EN
LO IN
R2
49.9
14 13
V
CC
9
10
11
12
4
3
2
1
5678
5571 F07
17
R3
49.9
C2
100nF
C1
100nF
RF
OUT
BBQM
BBQP
BOARD NUMBER: DC944A
J6
J3
J4
J5
R4
49.9
J2
BBMI
LT5571
BBPI V
CC
BBMQ GND
GND
BBPQ V
CC
GND
GND
RF
GND
GND
LO
GND
EN
GND
Figure 7. Evaluation Circuit Schematic
Figure 8. Component Side of Evaluation Board
Figure 9. Bottom Side of Evaluation Board
overheating. R1 (optional) limits the EN pin current in the
event that the EN pin is pulled high while the V
CC
inputs
are low. The application board PCB layouts are shown in
Figures 8 and 9.

LT5571EUF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Modulator / Demodulator 620 TO 1100 MHz Direct I/Q Modulator w/ High-Z Input, 0.5V DC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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