7©2018 Integrated Device Technology, Inc. February 12, 2018
VersaClock
®
6E - 5P49V60, 5P49V6965 and 5P49V6975 Evaluation Board User Guide
On-board Crystal
A 25MHz crystal is installed on the board with the 5P49V60 and 5P49V6965. If the evaluation board is assembled with a 5P49V6975, no
crystal is assembled because the crystal is integrated in the device. The crystal pins on the 5P49V6975 are NC (no connect).
Figure 6. Crystal Circuit
The board is shipped with a small 25MHz SMD crystal installed. The crystal can be replaced with a different frequency if needed. Note
that Output 1 with the default or “test” mode will only work when using a 25MHz crystal.
A thru-hole crystal can be assembled in the X1 position. Remove the small 25MHz crystal and also assemble the resistors R78 and R79
to connect the thru-hole crystal.
Another useful modification can be to remove the 25MHz crystal and assemble C6 to connect the SMA connector J6. Now a clock from a
generator or other source can be used to drive the XIN pin. Also assemble R17 when termination of the external clock is needed. Please
look up the requirements for the XIN amplitude in the device datasheet. Essentially, the amplitude on XIN should not exceed 1.2Vpp and
we recommend using 1.0Vpp for most tests. When doing phase noise measurements of the output clocks, use a very low noise clock for
XIN. The best phase noise at the outputs is achieved when using a crystal. Only the very best of low noise RF signal generators
connected to XIN can result in the same phase noise performance.
8©2018 Integrated Device Technology, Inc. February 12, 2018
VersaClock
®
6E - 5P49V60, 5P49V6965 and 5P49V6975 Evaluation Board User Guide
Configuration and Setup
1. Set SEL pin (pin 8) of DIP switch (U2) to “O” to select I
2
C mode.
2. Connect J18 to a USB port of the PC, using the supplied I
2
C cable.
3. Launch VersaClock 6E Timing Commander software (refer to VersaClock 6E Timing Commander User Guide).
4. Following the Getting Started steps in the Timing Commander software, an I
2
C connection is established between the GUI software
and the VersaClock 6E chip.
5. Select “Open Settings File” if you have existing settings or “New Settings File” and select the VersaClock 6E device depending on your
evaluation board. In the same screen, browse for a personality file, by clicking on the button at the bottom right, to be used with the
evaluation board.
6. Connect to the EVB by clicking on the microchip icon located at the top right of the Timing Commander screen.
7. Once connected, new options will be available on a green background indicating that the EVB has successfully connected with the
board. Write settings to the chip by clicking on the write all registers to the chip option.
8. All intended outputs should now be available for measurement.
9©2018 Integrated Device Technology, Inc. February 12, 2018
VersaClock
®
6E - 5P49V60, 5P49V6965 and 5P49V6975 Evaluation Board User Guide
Schematics
Evaluation board schematics are shown on the following pages.
Figure 7. VersaClock 6E Evaluation Board Schematics – page 1
R107 150_1%
R132 150_1%
Place unconnected pads of R38 and R47 close to pad
of C11 and unconnected pads of R40 and R48 close to
C13 to enable potential solder bridge.
R133 0
GND
VDDO4
Place unconnected pads of R139 and R140 close to pad
of C12 and unconnected pads of R138 and R141 close to
C14 to enable potential solder bridge.
OUT4
VDDO4
OUT3B
OUT3
OUT4B
VDDO2
VDDO2
VDDO1
VDDO1
VDDO0
OUT0_SELB_I2C
VDDO0
XO U T{3}
XI N{3}
XO U T
XI N
SEL0_SCL{3,5}
SEL1_SDA{2,3,5}
SD_OE{3}
SEL1_SDA
SD_OE
SEL0_SCL
R9 33
C11
0.1uF
C13
0.1uF
C7
0.1uF
C8
0.1uF
CLKINB{3}
CLKSEL{3}
CLKIN{3}
C9
0.1uF
C10
0.1uF
Place 33 OHM Resistors Closed to Main Device For CMOS and HCSL TERMINATION
5P49V6965 CONNECTIONS
Place AC Coupling Capacitors Close to SMA
C4
0.1uF
GND
J3
OUT0_SELB_I2C
GND
R8
125_NP
R14
84_NP
OUT0_SELB_I2C{3}
VDDO0
U1
5P49V6965A
XO U T
3
XI N / R E F
4
CLKIN
1
CLKINB
2
CLKSEL
6
SEL1/SDA
8
SEL0/SCL
9
SD/OE
7
VDDA
5
VDDD
22
VDDO0
23
OUT0_SEL_I2CB
24
VDDO1
21
OUT1
20
OUT1B
19
VDDO2
18
OUT2
17
OUT2B
16
VDDO3
15
OUT3
14
OUT3B
13
VDDO4
10
OUT4
11
OUT4B
12
EPAD1
25
EPAD2
26
EPAD3
27
EPAD4
28
EPAD5
29
EPAD6
30
EPAD7
31
EPAD8
32
EPAD9
33
Place R37 & R43 33 OHM Resistors Closed to Main Device For HCSL TERMINATION
R45 & R46 Should Closer to the SMA
OUT1
OUT1B
J8
J7
C12
0.1uF
C14
0.1uF
RECEIVER
GND
R39 33
RECEIVER
RECEIVER
VDDA
RECEIVER
OUT2B
OUT2
J14
3.3V LVPECL TERMINATION
J12
R108 DNP
J10
GND
OUT4
J9
OUT4B
R44 33
GND
R82 DNP
R83 DNP
GND
OUT3B
OUT3
2.5V and 3.3V HCSL TERMINATION
J13
J11
GND
R37 33
CMOS TERMINATION
R43 33
R45
DNP
R46
DNP
GND
GND
VDDO1
R18
125_NP
LVDS TERMINATION
R19
125_NP
R23
84_NP
R24
84_NP
GND
VDDO2
R30
125_NP
R31
125_NP
R35
84_NP
R49
DNP
R36
84_NP
R6 10K
R50
DNP
GND
VDDO3
OUT0_SELB_I2C_SW
R38
125_NP
OUT0_SELB_I2C_SW{3}
R40
125_NP
R47
84_NP
R48
84_NP
GND
GND
R138
125_NP
R139
125_NP
R140
84_NP
R141
84_NP
VDDO4
VDDO3
VDDO3
R127 0
OUT1
R128 0
OUT1B
R129 0
OUT2
R130 0
OUT2B
H2H1 H3 H4
VDDD
GND
Place R6=10K close to matched trace from R9 to C4
CLKIN
CLKINB
Stand Offs
CLKSEL
R143
DNP
Place unconnected pads of R30 and R35 close to pad
of C9 and unconnected pads of R31 and R36 close to
C10 to enable potential solder bridge.
Place unconnected pads of R8 and R14 close to
pad of C4 to enable potential solder bridge.
Place unconnected pads of R18 and R23 close to pad
of C7 and unconnected pads of R19 and R24 close to
C8 to enable potential solder bridge.
R144
DNP

5P49V6965-EVK

Mfr. #:
Manufacturer:
IDT
Description:
Clock & Timer Development Tools VersaClock 6E Standard Part EVK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet