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87421AMILF

P1-P3P4-P6P7-P9P10-P12P13-P15
÷1/÷2 Differential-to-LVDS
Clock Generator
87421
Data Sheet
©2016 Integrated Device Technology, Inc June 24, 20161
GENERAL DESCRIPTION
The 87421I is a high performance ÷1/÷2
Differential-to-LVDS Clock Generator. The CLK, nCLK
pair can accept most standard differential input
levels. The 87421I is characterized to operate from a 3.3V
power supply. Guaranteed part-to-part skew characteristics
make the 87421I ideal for those clock distribution applications
demanding well defi ned performance and repeatability.
FEATURES
• One differential LVDS output
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input lev-
els: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVDS levels with resistor bias on nCLK input
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.7ns (maximum)
• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
•
For functional replacement device use 87321
BLOCK DIAGRAM PIN ASSIGNMENT
87421I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
CLK
nCLK
MR
F_SEL
1
2
3
4
VDD
Q
nQ
GND
8
7
6
5
Q
nQ
CLK
nCLK
MR
F_SEL
0
1
÷1
÷2
R
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
87421 Data Sheet
©2016 Integrated Device Technology, Inc June 24, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3. FUNCTION TABLE
FIGURE 1A. ÷1 CONFIGURATION TIMING DIAGRAM
Number Name Type Description
1 CLK Input Pulldown Non-inverting differential clock input.
2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output (Q) to go low and the inverted output (nQ)
to go high. When logic LOW, the internal dividers and the output are
enabled. LVCMOS / LVTTL interface levels. See Table 3.
4 F_SEL Input Pulldown
Selects divider value for Q, nQ outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
5 GND Power Power supply ground.
6, 7 Q, nQ Output Differential output pair. LVDS interface levels.
8V
DD
Power Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
MR F_SEL Divide Value
1 X Reset: Q output low, nQ output high
00 ÷1
01 ÷2
CLK
MR
Q
FIGURE 1B. ÷2 CONFIGURATION TIMING DIAGRAM
87421 Data Sheet
©2016 Integrated Device Technology, Inc June 24, 20163
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, I
O
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, θ
JA
96°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 55 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 1.37 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.7 V
I
IH
Input High Current MR, F_SEL V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current MR, F_SEL V
DD
= 3.465V, V
IN
= 0V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK V
DD
= V
IN
= 3.465V 150 µA
nCLK V
DD
= V
IN
= 3.465V 5 µA
I
IL
Input Low Current
CLK V
DD
= 3.465V, V
IN
= 0V -5 µA
nCLK V
DD
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1
GND + 0.5 V
DD
- 0.85 V
NOTE 1: Common mode voltage is defi ned as V
IH
.
P1-P3P4-P6P7-P9P10-P12P13-P15

87421AMILF

Mfr. #:
Buy 87421AMILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PLL Based Clock Generator
Lifecycle:
New from this manufacturer.
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