87421AMILF Datasheet 87421AMILF, 87421AMILFT | P4-P6

87421 Data Sheet

TABLE 5. AC CHARACTERISTICS, V

= 3.3V±5%, TA = -40°C TO 85°C

TABLE 4D. LVDS DC CHARACTERISTICS, V

= 3.3V±5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CLK

Clock Input Frequency 1 GHz

Propagation Delay;

NOTE 1

CLK to Q (Dif) 1.0 1.7 ns

tsk(pp) Part-to-Part Skew; NOTE 2, 3 500 ps

JIT

Additive Phase Noise, RMS;

refer to Additive Phase Jitter Section

155.52MHz, Integration Range:

12kHz – 20MHz

0.17 ps

/ t

Output Rise/Fall Time 20% to 80% 150 500 ps

odc Output Duty Cycle f

< 500MHz 43 57 %

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 3: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Differential Output Voltage 350 470 540 mV

Δ V

Magnitude Change 50 mV

Offset Voltage 1.1 1.25 1.4 V

Δ V

Magnitude Change 50 mV

87421 Data Sheet

ADDITIVE PHASE JITTER

The spectral purity in a band at a speciﬁ c offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the speciﬁ ed plot in many applications. Phase

noise is deﬁ ned as the ratio of the noise power present in a 1Hz

band at a speciﬁ ed offset from the fundamental frequency to the

power value of the fundamental. This ratio is expressed in decibels

As with most timing speciﬁ cations, phase noise measurements have

issues. The primary issue relates to the limitations of the equipment.

Often the noise ﬂ oor of the equipment is higher than the noise ﬂ oor

(dBm) or a ratio of the power in the 1Hz band to the power in the

fundamental. When the required offset is speciﬁ ed, the phase noise

is called a dBc value, which simply means dBm at a speciﬁ ed offset

from the fundamental. By investigating jitter in the frequency domain,

we get a better understanding of its effects on the desired application

over the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

of the device. This is illustrated above. The device meets the noise

ﬂ oor of what is shown, but can actually be lower. The phase noise

is dependant on the input source and measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

Additive Phase Jitter @

155.52MHz (12kHz to 20MHz) = 0.17ps typical

87421 Data Sheet

PARAMETER MEASUREMENT INFORMATION

OUTPUT RISE/FALL TIME

DIFFERENTIAL INPUT LEVEL

3.3V OUTPUT LOAD AC TEST CIRCUIT

PART-TO-PART SKEW PROPAGATION DELAY

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

DIFFERENTIAL OUTPUT VOLTAGE SETUP

OFFSET VOLTAGE SETUP

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

87421AMILF

Mfr. #:

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Clock Generators & Support Products PLL Based Clock Generator

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87421AMILF

87421AMILF

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