IR3529
Page 16 of 22 February 12, 2010
APPLICATIONS SCHEMATIC
VRRDY
VID7
VID6
CVCCL
CC P1
CVDAC
RTCMP1
RVDAC
CVCCL2
VID7
1
VID6
2
VID5
3
VID4
4
VID3
5
VID2
6
SHIFT
30
VID1
7
VID0
8
ENABLE
9
HOTSET
11
VDAC
21
VDAC_BU FF
19
VRRDY
31
VSETPT
20
PHSIN
27
PHSOUT
26
EAOUT
16
FB
15
VDRP
17
IM ON
32
II N
29
SS/DEL
22
ROSC
23
VCCL
28
VN
18
VRHOT
10
VOSEN-
12
CLKOUT
25
PSI#
24
VOSEN+
13
VO
14
EXPAD
33
IR3503
VOUT-
RFB1
CFB
VOUT+
RDR P
RFB
CCS1
CCP
RSETPT
CSIN-
18
CSIN +
17
DACIN
3
GATEH
14
VCCL
12
VCC
16
PHSOUT
7
BOOST
13
PHSIN
5
PGND
9
ILL
1
EAIN
19
CLKIN
8
SW
15
GATEL
10
LGND
4
PSI#
2
SHIFT
6
OCSET
11
ISHAR E
20
IR3529
L1
COUT1
RC S1
RTCMP2
CBST1
RCP
CSS/D EL
ROCP1
+12V
RTCMP3
RTHER M
VID2
VID3
VID0
VID1
VID5
VID4
VOSEN+
VRHOT
VOSEN-
RHOTSET1
RHOTSET2
ROSC
PSI#
RMON1
CVCCL4
CCS3
CSIN-
18
CSIN+
17
DACIN
3
GATEH
14
VCCL
12
VCC
16
PHSOUT
7
BOOST
13
PHSIN
5
PGND
9
ILL
1
EAIN
19
CLKIN
8
SW
15
GATEL
10
LGND
4
PSI#
2
SHIF T
6
OCSET
11
ISHARE
20
IR3529
L3
CMON
RC S3
CBST3
RMON
CVCCL3
CCS2
L2
CSIN -
18
CSIN+
17
DACIN
3
GATEH
14
VCCL
12
VCC
16
PHSOUT
7
BOOST
13
PHSIN
5
PGND
9
ILL
1
EAIN
19
CLKIN
8
SW
15
GATEL
10
LGND
4
PSI#
2
SHIF T
6
OCSET
11
ISHARE
20
IR3529
RC S2
CBST2
IOUT
ENABLE
VOSEN-
CVCCL5
CCS4
L4
CSIN-
18
CSIN+
17
DACIN
3
GATEH
14
VCCL
12
VCC
16
PHSOUT
7
BOOST
13
PHSIN
5
PGND
9
ILL
1
EAIN
19
CLKIN
8
SW
15
GATEL
10
LGND
4
PSI#
2
SHIFT
6
OCSET
11
ISHARE
20
IR3529
RC S4
CBST4
ROCP2
COCP2
ROCP3
COCP3
COCP4
ROCP4
4.75V t o 7.5V VCCL
COCP1
VOSEN+
VOSEN-
Figure 9: Multi Phase Application Circuit
IR3529
Page 17 of 22 February 12, 2010
DESIGN PROCEDURES - IR3529
Inductor Current Sensing Capacitor C
CS
and Resistor R
CS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor R
CS
and capacitor
C
CS
in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage
across the capacitor C
CS
represents the inductor current. If the two time constants are not the same, the AC
component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch
does not affect the average current sharing among the multiple phases, but does affect the current signal IOUT as
well as the output voltage during the load current transient if adaptive voltage positioning is adopted.
Measure the inductance L and the inductor DC resistance R
L
. Pre-select the capacitor C
CS
and calculate R
CS
as
follows.
CS
L
CS
C
RL
R =
(1)
Bootstrap Capacitor C
BST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
A 0.1uF-1uF decoupling capacitor is required at the VCCL pin.
Current Share Loop Compensation
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at
least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated.
The crossover frequency of current share loop
is approximately 8 kHz
Cycle-by-Cycle Over Current Protection
Cycle-by-cycle over current protection helps to improve the transient response at load repetition rates closer to
the switching frequency of the VR. The over current threshold is programmed with an external resistor (R
OCSET
)
connected to the OCSET pin with a sink current of 200 µA. The OCSET comparator monitors the voltage across
the on-resistance (R
DS, ON
) of the high-side MOSFET and terminates the high side pulse if the sensed voltage
reaches the over current threshold. A capacitor (C
OCSET
) is used to reduce noise coupling into the OCSET pin of
the IC.
R
OCSET
=
(
)
µ
200
,*__ onRdsphaseperIload
where Iload_per_phase is the maximum current per phase which you do not want to exceed.
IR3529
Page 18 of 22 February 12, 2010
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout; therefore, minimizing the noise coupled to the IC.
Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and
power ground plane (PGND).
Separate analog bus (EAIN, DACIN, and IOUT) from digital bus (CLKIN, PSI, PHSIN, and PHSOUT) to
reduce the noise coupling.
Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to LGND and PGND planes
respectively through vias.
Place current sense resistors and capacitors (R
CS
and C
CS
) close to phase IC. Use Kelvin connection for the
inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor
terminal to CSIN- should not cross over the fast transition nodes, i.e., switching nodes, gate drive outputs,
and bootstrap nodes.
Place the decoupling capacitors C
VCC
and C
VCCL
as close as possible to VCC and VCCL pins of the phase
IC respectively.
Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of
the gate drive paths.
Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use
combination of different packages of ceramic capacitors.
There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output
capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load.
Route the switching power paths using wide and short traces or polygons; use multiple vias for connections
between layers.

IR3529MTRPBF

Mfr. #:
Manufacturer:
Infineon Technologies
Description:
Power Management Specialized - PMIC 2 CH OR 2 PHASE SYNC PWM CNTRLR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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