Integrated
Circuit
Systems, Inc.
853054AG www.icst.com/products/hiperclocks.html REV. A JANUARY 5, 2006
11
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853054.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853054 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V ± 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 61mA = 211.37mW
• Power (outputs)
MAX
= 27.83mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 211.37mW + 27.83mW = 239.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air flow of 200 meters per second and a multi-layer board, the appropriate value is 81.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.239W * 81.8°C/W = 104.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θ
JA
by Velocity (Meters per Second)
TABLE 6. THERMAL RESISTANCE
θθ
θθ
θ
JA
FOR 16-PIN TSSOP FORCED CONVECTION
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
