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ICS853054AGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Integrated
Circuit
Systems, Inc.
853054AG www.icst.com/products/hiperclocks.html REV. A JANUARY 5, 2006
7
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
PRELIMINARY
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
INPUTS:
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resister can be tied
from PCLK to ground.
RECOMMENDATIONS FOR UNUSED INPUT PINS
SELECT PINS:
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resister can be used.
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER TSD
IDT™ / ICS™ 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER ICS853054
7
Integrated
Circuit
Systems, Inc.
853054AG www.icst.com/products/hiperclocks.html REV. A JANUARY 5, 2006
8
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements. Figures 2A to 2E show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY
A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY
AN SSTL IN DRIVER
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY
A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY
A 3.3V LVDS DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY
A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCLK/nPCLK
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER TSD
IDT™ / ICS™ 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER ICS853054
8
Integrated
Circuit
Systems, Inc.
853054AG www.icst.com/products/hiperclocks.html REV. A JANUARY 5, 2006
9
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
PRELIMINARY
V
CC
- 2V
50Ω 50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT
FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω 125Ω
84Ω 84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. Figures 3A and 3B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
FIGURE 3B. LVPECL OUTPUT T ERMINATIONFIGURE 3A. LVPECL OUTPUT T ERMINATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER TSD
IDT™ / ICS™ 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER ICS853054
9
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ICS853054AGLFT

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IC CLK MULTPX 4:1 3.2GHZ 16TSSOP
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