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LT3011EMSE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LT3011
10
3011f
APPLICATIONS INFORMATION
in a small package, but they tend to have strong voltage
and temperature coeffi cients, as shown in Figures 2 and 3.
When used with a 5V regulator, a 16V 10μF Y5V capacitor
can exhibit an effective value as low as 1μF to 2μF for the
DC bias voltage applied and over the operating tempera-
ture range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is avail-
able in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitance change over temperature. Capacitance change
due to DC bias with X5R and X7R capacitors is better than
Y5V and Z5U capacitors, but can still be signifi cant enough
to drop capacitor values below appropriate levels. Capaci-
tor DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operating
voltage should be verifi ed.
Voltage and temperature coeffi cients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress, simi-
lar to the way piezoelectric accelerometer or microphone
works. For a ceramic capacitor, the stress can be induced
by vibrations in the system or thermal transients.
PWRGD Flag and Timing Capacitor Delay
The PWRGD fl ag is used to indicate that the ADJ pin volt-
age is within 10% of the regulated voltage. The PWRGD
pin is an open-collector output, capable of sinking 50μA
of current when the ADJ pin voltage is low. There is no
internal pull-up on the PWRGD pin; an external pull-up
resistor must be used. When the ADJ pin rises to within
10% of its fi nal reference value, a delay timer is started.
At the end of this delay, programmed by the value of the
capacitor on the C
T
pin, the PWRGD pin switches to a high
impedance and is pulled up to a logic level by an external
pull-up resistor.
To calculate the capacitor value on the C
T
pin, use the
following formula:
C
It
VV
TIME
CT DELAY
CT HIGH CT L OW
=
−
•
() ()
Figure 4 shows a block diagram of the PWRGD circuit. At
start-up, the timing capacitor is discharged and the PWRGD
pin will be held low. As the output voltage increases and
the ADJ pin crosses the 90% threshold, the JK fl ipfl op is
reset, and the 3μA current source begins to charge the
timing capacitor. Once the voltage on the C
T
pin reaches
the V
CT(HIGH)
threshold (approximately 1.7V at 25°C), the
capacitor voltage is clamped and the PWRGD pin is set to
a high impedance state.
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3011 F02
20
0
–20
–40
–60
–80
–100
0
4
8
10
26
12
14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10MF
TEMPERATURE (oC)
–50
40
20
0
–20
–40
–60
–80
–100
25 75
3011 F03
–25 0
50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10MF
Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics
LT3011
11
3011f
During normal operation, an internal glitch fi lter will ignore
short transients (<15μs). Longer transients below the 90%
threshold will reset the JK fl ip-fl op. This fl ip-fl op ensures
that the capacitor on the C
T
pin is quickly discharged all
the way to the V
CT(LOW)
threshold before restarting the
time delay. This provides a consistent time delay after the
ADJ pin is within 10% of the regulated voltage before the
PWRGD pin switches to high impedance.
Thermal Considerations
The power handling capability of the device will be limited by
the maximum rated junction temperature (125°C, LT3011E/
LT3011I or 150°C, LT3011H). The power dissipated by the
device will be made up of two components:
1. Output current multiplied by the input/output voltage
differential: I
OUT
• (V
IN
– V
OUT
) and,
2. GND pin current multiplied by the input voltage:
I
GND
• V
IN
The GND pin current is found by examining the GND pin
current curves in the Typical Performance Characteristics
section. Power dissipation will be equal to the sum of the
two components listed above.
The LT3011 series regulators have internal thermal limiting
designed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C (LT3011E/ LT3011I) or 150°C
(LT3011H) must not be exceeded. It is important to give
careful consideration to all sources of thermal resistance
from junction to ambient. Additional heat sources mounted
nearby must also be considered.
QJ
K
V
REF
• 90%
ADJ
V
CT(LOW)
z0.1V
V
CT(HIGH)
– V
BE
(z1.1V)
I
CT
3μA
C
T
3011 F04
–
+
–
+
PWRGD
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
The following table lists thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
Table 1. MSOP Measured Thermal Resistance
COPPER AREA
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE BACKSIDE
2500 sq mm 2500 sq mm 2500 sq mm 52°C/W
1000 sq mm 2500 sq mm 2500 sq mm 54°C/W
225 sq mm 2500 sq mm 2500 sq mm 58°C/W
100 sq mm 2500 sq mm 2500 sq mm 64°C/W
Table 2. DFN Measured Thermal Resistance
COPPER AREA
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE BACKSIDE
2500 sq mm 2500 sq mm 2500 sq mm 52°C/W
1000 sq mm 2500 sq mm 2500 sq mm 54°C/W
225 sq mm 2500 sq mm 2500 sq mm 58°C/W
100 sq mm 2500 sq mm 2500 sq mm 64°C/W
The thermal resistance junction-to-case (θ
JC
), measured
at the Exposed Pad on the back of the die, is 16°C/W.
Continuous operation at large input/output voltage dif-
ferentials and maximum load current is not practical due
to thermal limitations. Transient operation at high input/
output differentials is possible. The approximate thermal
time-constant for a 2500sq mm 3/32" FR-4 board, with
maximum topside and backside area for one ounce cop-
per, is three seconds. This time-constant will increase as
more thermal mass is added (i.e., vias, larger board and
other components).
For an application with transient high power peaks, average
power dissipation can be used for junction temperature
calculations as long as the pulse period is signifi cantly less
than the thermal time constant of the device and board.
Figure 4. PWRGD Circuit Block Diagram
APPLICATIONS INFORMATION
LT3011
12
3011f
Calculating Junction Temperature
Example 1: Given an output voltage of 5V, an input volt-
age range of 24V to 30V, an output current range of 0mA
to 50mA, and a maximum ambient temperature of 50°C,
what will the maximum junction temperature be?
The power dissipated by the device will be equal to:
I
OUT(MAX)
• (V
IN(MAX)
– V
OUT
) + (I
GND
• V
IN(MAX)
)
Where:
I
OUT(MAX)
= 50mA
V
IN(MAX)
= 30V
I
GND
at (I
OUT
= 50mA, V
IN
= 30V) = 1mA
So:
P = 50mA • (30V – 5V) + (1mA • 30V) = 1.28W
The thermal resistance will be in the range of 52°C/W to
64°C/W depending on the copper area. So, the junction
temperature rise above ambient will be approximately
equal to:
1.28W • 58°C/W = 74°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T
JMAX
= 50°C + 74°C = 124°C
Example 2: Given an output voltage of 5V, an input voltage
of 48V that rises to 72V for 5ms (max) out of every 100ms,
and a 5mA load that steps to 50mA for 50ms out of every
250ms, what is the junction temperature rise above ambi-
ent? Using a 500ms period (well under the time-constant
of the board), power dissipation is as follow:
P1 (48V
IN
, 5mA load) = 5mA • (48V – 5V)
+ (200μA • 48V) = 0.23W
P2 (48V
IN
, 50mA load) = 50mA • (48V – 5V)
+ (1mA • 48V) = 2.20W
P3 (72V
IN
, 5mA load) = 5mA (72V – 5V)
+ (200μA • 72V) = 0.35W
P1 (72V
IN
, 50mA load) = 50mA (72V – 5V)
+ (1mA • 72V) = 3.42W
Operation at the different power levels is as follows:
76% operation at P1, 19% for P2, 4% for P3,
and 1% for P4.
P
EFF
= 76%(0.23W) + 19%(2.20W) + 4%(0.35W)
+ 1%(3.42W) = 0.64W
With a thermal resistance in the range of 52°C/W to 64°C/W,
this translates to a junction temperature rise above ambi-
ent of 33°C to 41°C.
High Temperature Operation
Care must be taken when designing LT3011 applications to
operate at high ambient temperatures. The LT3011 works
at elevated temperatures but erratic operation can occur
due to unforeseen variations in external components. Some
tantalum capacitors are available for high temperature
operation, but ESR is often several ohms; capacitor ESR
above 3Ω is unsuitable for use with the LT3011. Ceramic
capacitor manufacturers (Murata, AVX, TDK and Vishay
Vitramon at this writing) now offer ceramic capacitors that
are rated to 150°C using an X8R dielectric. Device instability
will occur if the output capacitor value and ESR are outside
design limits at elevated temperature and operating DC
voltage bias (see information on capacitor characteristics
under Output Capacitance and Transient Response). Check
each passive component for absolute value and voltage
ratings over the operating temperature range.
Leakage in capacitors, or from solder fl ux left after insuf-
fi cient board cleaning, adversely affects the low quies-
cent current operation. Consider junction temperature
increase due to power dissipation in both the junction
and nearby components to ensure maximum specifi ca-
tions are not violated for the LT3011E/LT3011H/LT3011I
or external components.
Protection Features
The LT3011 incorporates several protection features which
make it ideal for use in battery-powered circuits. In ad-
dition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
limiting, the device is protected against reverse-input
voltages, and reverse voltages from output-to-input.
APPLICATIONS INFORMATION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LT3011EMSE#PBF

Mfr. #:
Buy LT3011EMSE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators 50mA, 3V to 80V Low Dropout Micropower Linear Regulator with PWRGD
Lifecycle:
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