LT3011
8
3011f
PIN FUNCTIONS
OUT (Pin 1/Pin 2): Output. The output supplies power to
the load. A minimum output capacitor of 1μF is required
to prevent oscillations. Larger capacitors will be required
for applications with large transient loads to limit peak
voltage transients. See the Applications Information
section for more information on output capacitance and
reverse output characteristics.
ADJ (Pin 2/Pin 3): Adjust. This is the input to the error
amplifi er. This pin is internally clamped to ±7V. It has a
bias current of 30nA which fl ows into the pin (see the
curve labeled ADJ Pin Bias Current vs Temperature in the
Typical Performance Characteristics section). The ADJ
pin voltage is 1.24V referenced to ground, and the output
voltage range is 1.24V to 60V.
GND (Pins 3, 11/Pins 4, 13): Ground. The exposed back-
side of the package (Pin 11/Pin 13) is an electrical connec-
tion for GND. As such, to ensure optimum device opera-
tion and thermal performance, the Exposed Pad must be
connected directly to Pin 3/Pin 4 on the PC board.
NC (Pins 4, 7, 9/Pins 1, 5, 8, 10, 12): No Connection.
These pins have no internal connection. Connecting NC
pins to a copper area for heat dissipation provides a small
improvement in thermal performance.
PWRGD (Pin 5/Pin 6): Power Good. The PWRGD fl ag is
an open-collector fl ag to indicate that the output voltage
has increased above 90% of the nominal output voltage.
There is no internal pull-up on this pin; a pull-up resistor
must be used. The PWRGD pin will change state from an
open-collector pull-down to high impedance after both
the output is above 90% of the nominal voltage and the
capacitor on the C
T
pin has charged through a 1.67V dif-
ferential. The maximum pull-down current of the PWRGD
pin in the low state is 50μA.
C
T
(Pin 6/Pin 7): Timing Capacitor. The C
T
pin allows the
use of a small capacitor to delay the timing between the
point where the output crosses the PWRGD threshold and
the PWRGD fl ag changes to a high impedance state. Cur-
rent out of this pin during the charging phase is 3μA. The
voltage difference between the PWRGD low and PWRGD
high states is 1.67V (see the Applications Information
section).
SHDN (Pin 8/Pin 9): Shutdown. The SHDN pin is used
to put the LT3011 into a low power shutdown state. The
output will be off when the SHDN pin is pulled low. The
SHDN pin can be driven either by 5V logic or open-collector
logic with a pull-up resistor. The pull-up resistor is only
required to supply the pull-up current of the open-collec-
tor gate, normally several microamperes. If unused, the
SHDN pin must be tied to a logic high or V
IN
.
IN (Pin 10/Pin 11): Input. Power is supplied to the device
through the IN pin. A bypass capacitor is required on this
pin if the device is more than six inches away from the
main input fi lter capacitor. In general, the output imped-
ance of a battery rises with frequency, so it is advisable to
include a bypass capacitor in battery-powered circuits. A
bypass capacitor in the range of 1μF to 10μF is suffi cient.
The LT3011 is designed to withstand reverse voltages
on the IN pin with respect to ground and the OUT pin. In
the case of a reverse input voltage, which can occur if a
battery is plugged in backwards, the LT3011 will act as if
there is a diode in series with its input. There will be no
reverse current fl ow into the LT3011 and no reverse volt-
age will appear at the load. The device will protect both
itself and the load.
Exposed Pad (Pin 11/Pin 13): Ground. The Exposed Pad
must be soldered to the PCB.
(DFN/MSOP)
