2003 Jun 25 17
Philips Semiconductors Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
74HC595; 74HCT595
Family 74HCT
GND = 0 V; t
r
=t
f
= 6 ns; C
L
=50pF.
SYMBOL PARAMETER
TEST CONDITIONS
MIN. TYP. MAX. UNIT
WAVEFORMS V
CC
(V)
T
amb
=25°C
t
PHL
/t
PLH
propagation delay
SH_CP to Q7’
see Fig.7 4.5 − 25 42 ns
propagation delay
ST_CP to Qn
see Fig.8 4.5 − 24 40 ns
t
PHL
propagation delay
MR to Q7’
see Fig.10 4.5 − 23 40 ns
t
PZH
/t
PZL
3-state output enable time
OE to Qn
see Fig.11 4.5 − 21 35 ns
t
PHZ
/t
PLZ
3-state output disable time
OE to Qn
see Fig.11 4.5 − 18 30 ns
t
W
shift clock pulse width
HIGH or LOW
see Fig.7 4.5 16 6 − ns
storage clock pulse width
HIGH or LOW
see Fig.8 4.5 16 5 − ns
master reset pulse width
LOW
see Fig.10 4.5 20 8 − ns
t
su
set-up time DS to SH_CP see Fig.9 4.5 16 5 − ns
set-up time
SH_CP to ST_CP
see Fig.8 4.5 16 8 − ns
t
h
hold time DS to SH_CP see Fig.9 4.5 +3 −2 − ns
t
rem
removal time
MR to SH_CP
see Fig.10 4.5 +10 −7 − ns
f
max
maximum clock
pulse frequency
SH_CP or ST_CP
see Figs 7 and 8 4.5 30 52 − MHz
T
amb
= −40 to +85 °C
t
PHL
/t
PLH
propagation delay
SH_CP to Q7’
see Fig.7 4.5 −−53 ns
propagation delay
ST_CP to Qn
see Fig.8 4.5 −−50 ns
t
PHL
propagation delay
MR to Q7’
see Fig.10 4.5 −−50 ns
t
PZH
/t
PZL
3-state output enable time
OE to Qn
see Fig.11 4.5 −−44 ns
t
PHZ
/t
PLZ
3-state output disable time
OE to Qn
see Fig.11 4.5 −−38 ns
