LTC3209-1/LTC3209-2
15
320912fa
START and STOP Conditions
A bus-master signals the beginning of a communication to
a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high. When the master has
finished communicating with the slave, it issues a STOP
condition by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I
2
C device.
Byte Format
Each byte sent to the LTC3209-1/LTC3209-2 must be
8 bits long followed by an extra clock cycle for the
Acknowledge bit to be returned by the LTC3209-1/LTC3209-
2. The data should be sent to the LTC3209-1/LTC3209-2
most significant bit (MSB) first.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active low)
generated by the slave (LTC3209-1/LTC3209-2) lets the
master know that the latest byte of information was
received. The Acknowledge related clock pulse is
generated by the master. The master releases the SDA
line (high) during the Acknowledge clock cycle. The
slave-receiver must pull down the SDA line during the
Acknowledge clock pulse so that it remains a stable low
during the high period of this clock pulse.
Slave Address
The LTC3209-1/LTC3209-2 responds to only one 7-bit
address which has been factory programmed to 0011011.
The eighth bit of the address byte (R/W) must be 0 for the
LTC3209-1/LTC3209-2 to recognize the address since it is
a write only device. This effectively forces the address to
be 8 bits long where the least significant bit of the address
is 0. If the correct seven bit address is given but the R/W
bit is 1, the LTC3209-1/LTC3209-2 will not respond.
OPERATIO
U
Bus Write Operation
The master initiates communication with the LTC3209-1/
LTC3209-2 with a START condition and a 7-bit address
followed by the Write Bit R/W = 0. If the address matches
that of the LTC3209-1/LTC3209-2, the part returns an
Acknowledge. The master should then deliver the most
significant data byte. Again the LTC3209-1/LTC3209-2
acknowledges and cycle is repeated two more times for a
total of one address byte and three data bytes. Each data
byte is transferred to an internal holding latch upon the
return of an Acknowledge. After all three data bytes have
been transferred to the LTC3209-1/LTC3209-2, the
master may terminate the communication with a STOP
condition. Alternatively, a REPEAT-START condition can
be initiated by the master and another chip on the I
2
C bus
can be addressed. This cycle can continue indefinitely and
the LTC3209-1/LTC3209-2 will remember the last input of
valid data that it received. Once all chips on the bus
have been addressed and sent valid data, a global STOP
condition can be sent and the LTC3209-1/LTC3209-2 will
update all registers with the data that it had received.
In certain circumstances the data on the I
2
C bus may
become corrupted. In these cases the LTC3209-1/
LTC3209-2 responds appropriately by preserving only the
last set of complete data that it has received. For example,
assume the LTC3209-1/LTC3209-2 has been successfully
addressed and is receiving data when a STOP condition
mistakenly occurs. The LTC3209-1/LTC3209-2 will ignore
this STOP condition and will not respond until a new
START condition, correct address, new set of data and
STOP condition are transmitted.
Likewise, if the LTC3209-1/LTC3209-2 was previously
addressed and sent valid data but not updated with a
STOP, it will respond to any STOP that appears on the bus
with only one exception, independent of the number of
REPEAT-STARTs that have occurred. If a REPEAT-START
is given and the LTC3209-1/LTC3209-2 successfully
acknowledges its address, it will not respond to a STOP
until all bytes of the new data have been received
and acknowledged.
