Data Sheet ADL5544
Rev. A | Page 15 of 20
25
0
5
10
15
20
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FREQUENCY (GHz)
NOISE FIGURE, DEFAULT SETUP CONFIGURATION
NOISE FIGURE, HIGH FREQUENCY CONFIGURATION
P1dB, DEFAULT SETUP CONFIGURATION
P1dB, HIGH FREQUENCY CONFIGURATION
GAIN, DEFAULT SETUP CONFIGURATION
GAIN, HIGH FREQUENCY CONFIGURATION
OIP3, DEFAULT SETUP CONFIGURATION
OIP3, HIGH FREQUENCY CONFIGURATION
11384-031
Figure 32. Noise Figure, Gain, P1dB, and OIP3 vs. Frequency,
4 GHz to 6 GHz, Comparison of Performance
with the Optimized Settings and the Default Configuration
0
–5
–10
–15
–20
–30
–25
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
S-PARAMETERS (dB)
FREQUENCY (GHz)
S11, DEFAULT SETUP CONFIGURATION
S11, HIGH FREQUENCY CONFIGURATION
S12, DEFAULT SETUP CONFIGURATION
S12, HIGH FREQUENCY CONFIGURATION
S22, DEFAULT SETUP CONFIGURATION
S22, HIGH FREQUENCY CONFIGURATION
11384-032
Figure 33. Return Loss and Reverse Isolation, 4 GHz to 6 GHz,
Comparison of Performance with the Optimized Settings
and the Default Configuration
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 34 shows the recommended land pattern for the
ADL5544. To minimize thermal impedance, the exposed pad
on the underside of the SOT-89 package is soldered to a ground
plane, along with Pin 2. If multiple ground layers exist, stitch
the layers together using vias.
1.50mm
3.00mm
1.27mm
0.62mm
3.48mm
1.80mm
0.86mm
5.37mm
0.20mm
0.762mm
0.635mm
0.86mm
11384-101
Figure 34. Recommended Land Pattern
The land pattern on the ADL5544 evaluation board provides a
measured thermal resistance
JA
) of 53°C/W. To measure θ
JA
,
the temperature at the top of the SOT-89 package is found with
an IR temperature gun. Thermal simulation suggests a junction
temperature 10°C higher than the top-of-package temperature.
With additional measurements of the ambient temperature and
I/O power, θ
JA
can be determined.
ADL5544 Data Sheet
Rev. A | Page 16 of 20
OPERATION DOWN TO 30 MHz
To operate the ADL5544 at frequencies below 100 MHz, a feed-
back network must be implemented between the input and output
ports of the device to ensure stability. Figure 35 shows a sample
configuration used to evaluate the device at frequencies below
100 MHz. Figure 36 to Figure 38 demonstrate the performance
of the device in this configuration.
RFIN
GND
GND
RFOUT
1
2
(2)
3
ADL5544
L1
1000nH
V
POS
GND
RFIN
C1
100nF
RFOUT
C2
100nF
C6
10µF
C5
1nF
C4
100pF
R
F
1500Ω
C
F
10nF
11384-034
Figure 35. Setup for Low Frequency Operation Down to 30 MHz
40
35
0
5
10
15
20
25
30
30 40 50 60 70 80 90 100
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FREQUENCY (MHz)
P1dB
OIP3
GAIN
NOISE FIGURE
11384-035
Figure 36. Noise Figure, Gain, P1dB, and OIP3 vs. Frequency,
30 MHz to 100 MHz
0
–5
–10
–15
–20
–30
–25
30 40 50 60 70 80 90 100
S-PARAMETERS (dB)
FREQUENCY (MHz)
S11
S12
S22
11384-036
Figure 37. Return Loss and Reverse Isolation, 30 MHz to 100 MHz
32
31
30
29
28
27
26
–9 –7 –5 –3 –1
OIP3 (dBm)
P
OUT
PER TONE (dBm)
+25°C
+85°C
+105°C
–40°C
11384-037
Figure 38. OIP3 vs. P
OUT
at 30 MHz
W-CDMA ACPR PERFORMANCE
Figure 39 shows a plot of the adjacent channel power ratio
(ACPR) vs. P
OUT
for the ADL5544. The signal type used is a
single wideband code division multiple access (W-CDMA)
carrier (Test Model 1-64) at 2140 MHz. This signal is generated
by a very low ACPR source. ACPR is measured at the output by
a high dynamic range spectrum analyzer that incorporates an
instrument noise-correction function.
0
–80
–70
–60
–50
–40
–30
–20
–10
–20 –15 –10 –5 0 5
ACPR @ 5MHz CARRIER OFFSET (dBc)
P
OUT
(dBm)
11384-038
Figure 39. ACPR vs. P
OUT
, Single W-CDMA Carrier (Test Model 1-64)
at 2140 MHz
The ADL5544 achieves an ACPR of −80 dBc at an output power
level of −7 dBm, at which point device noise and not distortion
begins to dominate the power in the adjacent channels. At an
output power level of 0 dBm, ACPR is still very low at −63 dBc.
Data Sheet ADL5544
Rev. A | Page 17 of 20
EVALUATION BOARD
Figure 40 shows the ADL5544 evaluation board layout.
Figure 41 shows the schematic for the evaluation board.
The board is powered by a single 5 V supply. Table 7 lists
the components used on the evaluation board. Power can
be applied to the board through clip-on leads (V
SUP
, GND).
11384-039
Figure 40. Evaluation Board Layout (Top)
RFIN
GND
GND
RFOUT
1
2
(2)
3
ADL5544
L1
100nH
V
SUP
GND
RFIN
C1
100pF
RFOUT
C2
100pF
C6
10µF
C5
1nF
C4
100pF
11384-040
Figure 41. Evaluation Board Schematic
Table 7. Evaluation Board Configuration Options
Component Function Default Value
C1, C2 AC coupling capacitors 100 pF, 0402
L1 DC bias inductor 100 nH, 0603 (Coilcraft 0603HP or equivalent)
V
SUP
and GND Clip-on terminals for power supply
C4, C5, C6 Power supply decoupling capacitors
C4: 100 pF, 0603
C5: 1 nF, 0603
C6: 10 μF, 1206

ADL5544-EVALZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Development Tools ADL5544 EVAL BRD
Lifecycle:
New from this manufacturer.
Delivery:
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