85222AM-02LF

REVISION B 6/15/15
85222-02 DATA SHEET
7 1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 1.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DD_MAX
- V
OH_MAX
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
Pd_H = (1.4V/50Ω) * (3.465V - 1.4V) = 57.8mW
Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 82.3mW
FIGURE 1. HSTL DRIVER CIRCUIT AND TERMINATION
1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
85222-02 DATA SHEET
8 REVISION B 6/15/15
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 85222-02 is: 411
TABLE 6. θ
JA
VS. AIR FLOW TABLE 8 LEAD SOIC
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
REVISION B 6/15/15
85222-02 DATA SHEET
9 1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
SYMBOL
Millimeters
MINIMUM MAXIMUM
N8
A 1.35 1.75
A1 0.10 0.25
B 0.33 0.51
C 0.19 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BASIC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
α

85222AM-02LF

Mfr. #:
Manufacturer:
IDT
Description:
Translation - Voltage Levels 2 HSTL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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