DS599 (v1.1) April 3, 2007 www.xilinx.com 1
Product Specification
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Features
• AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade.
• Guaranteed to meet full electrical specifications over
T
A
= -40° C to +105° C with T
J
Maximum = +125° C
(Q-grade)
• 15.5 ns pin-to-pin logic delays
• System frequency up to 64.5 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
- 44-pin VQFP (34 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
- Pb-free package only
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
WARNING: Programming temperature range of
T
A
= 0° C to +70° C
Description
The XA9572XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage automotive applications. It is comprised
of four 54V18 Function Blocks, providing 1,600 usable
gates with propagation delays of 15.5 ns. See Figure 2 for
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. Each macrocell in an XA9500XL automotive device
must be configured for low-power mode (default mode for
XA9500XL devices). In addition, unused product-terms and
macrocells are automatically deactivated by the software to
further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC(0.052*PT + 0.272) + 0.04 * MC
TOG
* MC * f
where:
MC = # macrocells
PT = average number product terms per macrocell
f = maximum clock frequency
MC
TOG
= average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XA9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
0
XA9572XL Automotive CPLD
DS599 (v1.1) April 3, 2007
00
Product Specification
R
Figure 1: Typical I
CC
vs. Frequency for XA9572XL
Clock Freq uency ( M Hz)
Typical I
CC
(mA)
100
DS599_01_121106
25
50
75
50
0
64.5 MHz
