XA9572XL Automotive CPLD
DS599 (v1.1) April 3, 2007 www.xilinx.com 5
Product Specification
R
Internal Timing Parameters
Symbol Parameter
XA9572XL-15
UnitsMin Max
Buffer Delays
T
IN
Input buffer delay - 3.5 ns
T
GCK
GCK buffer delay - 1.8 ns
T
GSR
GSR buffer delay - 4.5 ns
T
GTS
GTS buffer delay - 7.0 ns
T
OUT
Output buffer delay - 3.0 ns
T
EN
Output buffer enable/disable delay - 0 ns
Product Term Control Delays
T
PTCK
Product term clock delay - 2.7 ns
T
PTSR
Product term set/reset delay - 1.8 ns
T
PTTS
Product term 3-state delay - 7.5 ns
Internal Register and Combinatorial Delays
T
PDI
Combinatorial logic propagation delay - 1.7 ns
T
SUI
Register setup time 3.0 - ns
T
HI
Register hold time 3.5 - ns
T
ECSU
Register clock enable setup time 3.0 - ns
T
ECHO
Register clock enable hold time 3.5 - ns
T
COI
Register clock to output valid time - 1.0 ns
T
AOI
Register async. S/R to output delay - 7.0 ns
T
RAI
Register async. S/R recover before clock 10.0 - ns
T
LOGI
Internal logic delay - 7.3 ns
Feedback Delays
T
F
Fast CONNECT II feedback delay - 4.2 ns
Time Adders
T
PTA
Incremental product term allocator delay - 1.0 ns
T
SLEW
Slew-rate limited delay - 4.5 ns
