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873995AYLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Differential-to-3.3V LVPECL
Zero Delay/Multiplier/Divider
873995
DATA SHEET
873995 REVISION A 8/25/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 873995 is a Zero Delay/Multiplier/Divider with hitless input clock
switching capability and a member of the family of low jitter/phase
noise devices from IDT. The 873995 is ideal for use in redundant,
fault tolerant clock trees where low phase noise and low jitter are
critical. The device receives two differential LVPECL clock signals
from which it generates 6 LVPECL clock outputs with “zero” delay.
The out-put divider and feedback divider selections also allow for
frequency multiplication or division.
The 873995 Dynamic Clock Switch (DCS) circuit continuously
monitors both input clock signals. Upon detection of a failure (input
clock stuck LOW or HIGH for at least 1 period), INP_BAD for that
clock will be set HIGH. If that clock is the primary clock, the DCS will
switch to the good secondary clock and phase/frequency alignment
will occur with minimal output phase disturbance.
The low jitter characteristics combined with input clock monitoring
and automatic switching from bad to good input clocks make the
873995 an ideal choice for mission criti-cal applications that utilize
1G or 10G Ethernet or 1G/4G/10G Fibre Channel.
FEATURES
• Six differential 3.3V LVPECL outputs
• Selectable differential clock inputs
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Input clock frequency range: 49MHz to 213.33MHz
• Output clock frequency range: 49MHz to 640MHz
• VCO range: 490MHz to 640MHz
• External feedback for “zero delay” clock regeneration
with confi gurable frequencies
• Output skew: 100ps (maximum)
• RMS phase jitter (1.875MHz - 20MHz): 0.77ps (typical) assum-
ing a low phase noise reference clock input
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Use replacement part 873996AYLF
PIN ASSIGNMENTBLOCK DIAGRAM
REVISION A 8/25/15
873995 DATA SHEET
2 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1 PLL_SEL Input Pullup
Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock.When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
2 nMR Input Pullup
Active LOW Master Reset. When logic LOW, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic HIGH, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
3 nINIT Input Pullup
When HIGH-to-LOW, resets the input bad fl ags and aligns CLK_INDI-
CATOR to SEL_CLK. LVCMOS / LVTTL interface levels.
4, 12, 17 V
EE
Power Negative supply pins.
5 CLK0 Input Pulldown Non-inverting differential clock input.
6 nCLK0 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left fl oating.
7 CLK1 Input Pulldown Non-inverting differential clock input.
8 nCLK1 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left fl oating.
9 EXT_FB Input Pulldown Differential external feedback.
10 nEXT_FB Input
Pullup/
Pulldown
Differential external feedback. V
CC
/2 default when left fl oating.
11 SEL_CLK Input Pulldown
Selects the primary reference clock. When LOW, selects CLK0 as the
primary clock source. When HIGH, selects CLK1 as the primary clock
source. LVCMOS / LVTTL interface levels.
13, 47 V
CC
Power Core supply pins.
14, 15, 16 NB0, NB1, NB2 Input Pullup Bank B output divider control pins. LVCMOS / LVTTL interface levels.
18, 19, 20 NA0, NA1, NA2 Input Pullup Bank A output divider control pins. LVCMOS / LVTTL interface levels.
21, 28 V
CCO_B
Power Output supply voltage for B Bank outputs.
22, 23 nQB2, QB2 Output Differential output pair. LVPECL interface levels.
24, 25 nQB1, QB1 Output Differential output pair. LVPECL interface levels.
26, 27 nQB0, QB0 Output Differential output pair. LVPECL interface levels.
29, 36 V
CCO_A
Power Output supply voltage for A Bank outputs.
30, 31 nQA2, QA2 Output Differential output pair. LVPECL interface levels.
32, 33 nQA1, QA1 Output Differential output pair. LVPECL interface levels.
34, 35 nQA0, QA0 Output Differential output pair. LVPECL interface levels.
37 V
CCO_FB
Power Output supply voltage for FB outputs.
38, 39 QFB, nQFB Output Feedback outputs. LVPECL interface levels.
40 V
CCA
Power Analog supply pin.
41, 42,
43
NFB0, NFB1, NFB2 Input Pullup Feedback divider control pins. LVCMOS / LVTTL interface levels.
44 CLK_INDICATOR Output
Clock indicator pin. When LOW, CLK0, nCLK0 is selected, when HIGH,
CLK1, nCLK1 is selected. LVCMOS / LVTTL interface levels.
45 INP0BAD Output
Indicates detection of a bad input reference clock 0 with respect to the
feedback signal. The output is active HIGH.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION A 8/25/15
873995 DATA SHEET
3 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
NFB[2:0] Feedback Divider Value Output Frequency Range
000 1 N/A
NOTE1
001 2 N/A
NOTE1
010 3 163.33MHz - 200MHz
011 4 122.5MHz - 160MHz
100 5 98MHz - 128MHz
101 6 81.66MHz - 106.66MHz
110 8 61.25MHz - 80MHz
111 10 49MHz - 64MHz
NOTE 1: The Phase Detector has a maximum frequency limit of 200MHz, so these values cannot be used for feedback. The
reason these options are available is for applications that use an output on Bank A or Bank B for feedback and the QFB/
nQFB pair for a high frequency output. For example, a user may need two 62.5MHz outputs, three 125MHz outputs and one
625MHz output from a 62.5MHz reference clock. For this case, the user would use one of the Bank A Outputs for feedback
and set the bank for /10, and use the other two Bank A Outputs to drive the 2 loads. The Bank B Output Divider would be set
for /5, and the Feedback Divider would be set for /1.
TABLE 3A. FEEDBACK DIVIDER FUNCTION TABLE
TABLE 3B. NA/NB BANK DIVIDER FUNCTION TABLE
NA[2:0], NB[2:0] Bank A/B Divider Value Output Frequency Range
000 1 490MHz - 640MHz
001 2 245MHz - 320MHz
010 3 163.33MHz - 213.33MHz
011 4 122.5MHz - 160MHz
100 5 98MHz - 128MHz
101 6 81.66MHz - 106.66MHz
110 8 61.25MHz - 80MHz
111 10 49MHz - 64MHz
TABLE 1. PIN DESCRIPTIONS, CONTINUED
Number Name Type Description
46 INP1BAD Output
Indicates detection of a bad input reference clock 1 with respect to the
feedback signal. The output is active HIGH.
LVCMOS / LVTTL interface levels.
48 MAN_OVERRIDE Input Pulldown
Manual override. When HIGH, disables internal clock switch circuitry
and CLK_INDICATOR will track SEL_CLK. When LOW, Dynamic Clock
Switch is enabled. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

873995AYLFT

Mfr. #:
Buy 873995AYLFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products 6 LVPECL OUT MUX
Lifecycle:
New from this manufacturer.
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