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873995AYLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
REVISION A 8/25/15
873995 DATA SHEET
10 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 873995 pro-
vides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
and V
CCOx
should
be individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To achieve opti-
mum jitter performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
CCA
pin.
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
CCA
10μF
.01μF
3.3V
.01μF
V
CC
POWER SUPPLY FILTERING TECHNIQUES
REVISION A 8/25/15
873995 DATA SHEET
11 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLKx /nCLKx accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both V
SWING and VOH must
meet the V
PP and VCMR input requirements. Figures 3A to 3D show
interface examples for the HiPerClockS CLKx/nCLKx input driven
by the most common driver types. The input interfaces suggested
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confi rm the driver termination requirements.
For example in Figure 3A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
INPUTS:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input, both
CLK and nCLK can be left fl oating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left fl oating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left fl oating or terminated.
REVISION A 8/25/15
873995 DATA SHEET
12 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50Ω transmission
FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 4A
and 4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
TERMINATION FOR LVPECL OUTPUTS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

873995AYLFT

Mfr. #:
Buy 873995AYLFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products 6 LVPECL OUT MUX
Lifecycle:
New from this manufacturer.
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