HEF4541B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5 — 15 December 2015 4 of 16
NXP Semiconductors
HEF4541B
Programmable timer
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[2] For correct power-on reset, the supply voltage should be above 8.5 V. For V
DD
< 8.5 V, disable the autoreset and connect AR to V
DD
.
[3] The timer is initialized on a reset pulse and the output changes state after 2
n-1
counts and remains in that state (latched). Reset of this
latch is obtained by master reset or by a LOW to HIGH transition on the MODE input.
7. Limiting values
[1] For SO14 package: P
tot
derates linearly with 8 mW/K above 70 C.
Table 3. Function table
[1]
Input MODE
AR MR PH MODE
H L X X auto reset disabled
L L X X auto reset enabled
[2]
XHXXmaster reset active
X L X H normal operation selected division to output
X L X L single-cycle mode
[3]
X L L X output initially LOW after reset
X L H X output initially HIGH, after reset
Table 4. Frequency selection table
A0 A1 Number of counter stages n
L L 13 8192
L H 10 1024
H L 8 256
H H 16 65536
f
OSC
f
O
---------- 2
n
=
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +18 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
DD
+ 0.5 V - 10 mA
V
I
input voltage 0.5 V
DD
+ 0.5 V
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
DD
+ 0.5 V - 10 mA
I
I/O
input/output current O output - 10 mA
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature 40 +85 C
P
tot
total power dissipation T
amb
= 40 C to +85 C
SO14 package
[1]
- 500 mW
P power dissipation - 100 mW
