HEF4541B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5 — 15 December 2015 6 of 16
NXP Semiconductors
HEF4541B
Programmable timer
I
OL
LOW-level
output current
CTC, RTC;
V
O
= 0.4 V 5 V 0.33 - 0.27 - 0.20 - mA
V
O
= 0.5 V 10 V 1.0 - 0.85 - 0.68 - mA
V
O
= 1.5 V 15 V 3.2 - 2.7 - 2.3 - mA
O;
V
O
= 0.4 V 5 V 0.64 - 0.5 - 0.36 - mA
V
O
= 0.5 V 10 V 1.6 - 1.3 - 0.9 - mA
V
O
= 1.5 V 15 V 4.2 - 3.2 - 2.4 - mA
I
I
input leakage
current
15 V - 0.1 - 0.1 - 1.0 A
I
DD
supply current I
O
= 0 A 5 V - 5 - 5 - 150 A
10 V - 10 - 10 - 300 A
15 V - 20 - 20 - 600 A
C
I
input capacitance - - - - 7.5 - - pF
Table 7. Static characteristics
…continued
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= 25 C T
amb
= 85 C Unit
Min Max Min Max Min Max
Table 8. Reset characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; see Table 12 for test conditions; unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= +25 C T
amb
= +85 C Unit
Min Max Min Typ Max Min Max
I
DD
supply current supply current for
power-on reset
enable;
AR
= MR = 0 V; Other
inputs at 0 V or V
DD
5 V - 80 - 20 80 - 230 A
10 V - 750 - 250 600 - 700 A
15 V - 1.6 - 0.5 1.3 - 1.5 mA
V
DD
supply voltage supply voltage for
automatic reset
initialization;
AR
= MR = 0 V; Other
inputs at 0 V or V
DD
---8.55---V
HEF4541B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5 — 15 December 2015 7 of 16
NXP Semiconductors
HEF4541B
Programmable timer
10. Dynamic characteristics
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
[2] t
pd
is the same as t
PHL
and t
PLH
.
[3] t
W
is the same as t
WL(min)
and t
WH(min)
.
Table 9. Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C unless otherwise specified. For test circuit, see Figure 5.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ
[1]
Max Unit
t
pd
propagation delay RS to O;
2
8
selected;
see Figure 4
5 V
[2]
348 ns + (0.55 ns/pF)C
L
- 375 750 ns
10 V 139 ns + (0.23 ns/pF)C
L
- 150 300 ns
15 V 102 ns + (0.16 ns/pF)C
L
- 110 220 ns
RS to O;
2
10
selected;
see Figure 4
5 V 398 ns + (0.55 ns/pF)C
L
- 425 850 ns
10 V 154 ns + (0.23 ns/pF)C
L
- 165 330 ns
15 V 112 ns + (0.16 ns/pF)C
L
- 120 240 ns
RS to O;
2
13
selected;
see Figure 4
5 V 483 ns + (0.55 ns/pF)C
L
- 510 1020 ns
10 V 179 ns + (0.23 ns/pF)C
L
- 190 380 ns
15 V 127 ns + (0.16 ns/pF)C
L
- 135 270 ns
RS to O;
2
16
selected;
see Figure 4
5 V 548 ns + (0.55 ns/pF)C
L
- 575 1150 ns
10 V 199 ns + (0.23 ns/pF)C
L
- 210 420 ns
15 V 142 ns + (0.16 ns/pF)C
L
- 150 300 ns
t
W
pulse width RS LOW;
MR HIGH;
see Figure 4
5 V
[3]
60 30 - ns
10 V 30 15 - ns
15 V 24 12 - ns
f
clk(max)
maximum clock
frequency
RS; see Figure 4 5 V 8 16 - MHz
10 V 15 30 - MHz
15 V 18 36 - MHz
f
osc
oscillator frequency R
t
= 5 k;
C
t
=1nF;
R
S
=10k;
see Figure 6
5 V - 90 - kHz
10 V - 90 - kHz
15 V - 90 - kHz
R
t
= 56 k;
C
t
=1nF;
R
S
= 120 k;
see Figure 6
5 V - 8 - kHz
10 V - 8 - kHz
15 V - 8 - kHz
HEF4541B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5 — 15 December 2015 8 of 16
NXP Semiconductors
HEF4541B
Programmable timer
[1] f
i
= input frequency in MHz; f
o
= output frequency in MHz; C
L
= output load capacitance in pF; V
DD
= supply voltage in V;
f
osc
= oscillator frequency in MHz; C
TC
= timing capacitance in pF.
11. Waveforms
Table 10. Dynamic power dissipation
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula
Per package
P
D
dynamic power dissipation 5 V P
D
= 1300 f
i
+ (f
o
C
L
V
DD
2
) W
10 V P
D
= 5300 f
i
+ (f
o
C
L
V
DD
2
) W
15 V P
D
= 12000 f
i
+ (f
o
C
L
V
DD
2
) W
Using the on-chip oscillator
P
D(Tot)
Total dynamic power dissipation 5 V P
D
= 1300 f
osc
+ f
o
C
L
V
DD
2
+ 2C
TC
V
DD
2
f
osc
+ 10V
DD
W
10 V P
D
= 5300 f
osc
+ f
o
C
L
V
DD
2
+ 2C
TC
V
DD
2
f
osc
+ 100V
DD
W
15 V P
D
= 12000 f
osc
+ f
o
C
L
V
DD
2
+ 2C
TC
V
DD
2
f
osc
+ 400V
DD
W
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Measurement are points given in Table 11
, the test circuit in Figure 5 and the test data in Table 12
(1) 2
n
pulses as selected by address inputs (A0, A1).
Fig 4. Propagation delay clock (RS) to output (O), clock pulse width and maximum clock frequency
9
,
9
66
9
2+
9
2/
9
,
9
66
W
:+PLQ
9
0
9
0
I
FONPD[
W
W
:/PLQ
W
3/+
W
3+/
Table 11. Measurement points
Supply voltage Input Output
V
DD
V
M
V
M
5 V to 15 V 0.5V
DD
0.5V
DD

HEF4541BP,652

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Timers & Support Products PROGRAMMABLE TIMER
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