IDT71T016SA12PH8

6.424
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
0V to 2.5V
1.5ns
(V
DD
/2)
(V
DD
/2)
See Figure 1, 2 and 3
5326 tbl 09
+1.25V
50
I/O
Z
0
=50
5326 drw 0
3
30pF
6.42
5
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
71T016SA10
(2)
71T016SA12 71T016SA15 71T016SA20
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 10
____
12
____
15
____
20
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
____
20 ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
____
20 ns
t
CL Z
(1 )
Chip Select Low to Output in Low-Z 4
____
4
____
5
____
5
____
ns
t
CHZ
(1 )
Chip Select Hig h to Output in High-Z
____
5
____
6
____
6
____
8ns
t
OE
Output Enable Low to Output Valid
____
5
____
6
____
7
____
8ns
t
OL Z
(1)
Output Enable Low to Output in Low-Z 0
____
0
____
0
____
0
____
ns
t
OHZ
(1 )
Output Enable High to Output in High-Z
____
5
____
6
____
6
____
8ns
t
OH
Output Hold from Address Change 4 4 4 4 ns
t
BE
Byte Enable Low to Output Valid 5 6 7
____
8ns
t
BL Z
(1 )
Byte Enable Low to Output in Low-Z 0
____
0
____
0
____
0
____
ns
t
BHZ
(1 )
Byte Enable High to Output in High-Z
____
5
____
6
____
6
____
8ns
WRITE CYCLE
t
WC
Write Cycle Time 10
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End of Write 7
____
8
____
10
____
12
____
ns
t
CW
Chip Select Low to End of Write 7
____
8
____
10
____
12
____
ns
t
BW
Byte Enable Low to End of Write 7
____
8
____
10
____
12
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WR
Address Hold from End of Write 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 7
____
8
____
10
____
12
____
ns
t
DW
Data Valid to End of Write 5
____
6
____
7
____
9
____
ns
t
DH
Data Hold Time 0
____
0
____
0
____
0
____
ns
t
OW
(1 )
Write Enable High to Output in Low-Z 3
____
3
____
3
____
3
____
ns
t
WHZ
(1 )
Write Enable Low to Output in High-Z
____
5
____
6
____
6
____
8ns
5326 tbl 10
Timing Waveform of Read Cycle No. 1
(1,2,3)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
NOTES:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 0
0
C to +70
0
C temperature range only.
6.426
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2
(1)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.

IDT71T016SA12PH8

Mfr. #:
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Description:
IC SRAM 1M PARALLEL 44TSOP II
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