MAX5741
10-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
10 ______________________________________________________________________________________
tents to the DAC latch. CS may then either be held low
or brought high. CS must be brought high for a mini-
mum of 80ns before the next write sequence, since a
write sequence is initiated on a falling edge of CS. Not
keeping CS low during the first 15 SCLK cycles dis-
cards input data. The serial clock (SCLK) can idle
either high or low between transitions.
The MAX5741 has two internal registers per DAC, the
input register and the DAC register. The input register
holds the data that is waiting to be shifted to the DAC
register. All four input registers can be loaded without
updating the output. This function is useful when all out-
puts need to be updated at the same time. The input
register can be made transparent. When the input reg-
ister is transparent, the data written into DIN loads
directly to the DAC register and the output is updated.
The DAC output is not updated until data is written to
the DAC register. See Table 2 for a list of serial-inter-
face programming commands.
Power-On Reset (POR)
The MAX5741 has an internal POR circuit. At power-up all
DACs are powered-down and OUT_ is terminated to
GND through 100kΩ resistors. Contents of input and DAC
registers are cleared to all zero. 8µs recovery time after
issuing a wake-up command is needed before writing to
the DAC registers. Power-down mode control commands
can be applied immediately with no recovery time.
C3–C0 are control bits. The data bits D9 to D0 are in
straight binary format. Set bits S1 and S0 to zero. All
zeros correspond to zero scale and all ones corre-
spond to full scale.
EXTENDED
CONTROL
DATA BITS
C3 C2 C1 C0 D9–D3 D2 D1 D0 S1 S0
DESCRIPTION FUNCTION
1111 X 00000 DAC A DAC O/P, wake-up
1111 X 00001 DAC A Floating output
1111 X 00010 DAC A Output is terminated with 1kΩ
1111 X 00011 DAC A Output is terminated with 100kΩ
1111 X 00100 DAC B DAC O/P, wake-up
1111 X 00101 DAC B Floating output
1111 X 00110 DAC B Output is terminated with 1kΩ
1111 X 00111 DAC B Output is terminated with 100kΩ
1111 X 01000 DAC C DAC O/P, wake-up
1111 X 01001 DAC C Floating output
1111 X 01010 DAC C Output is terminated with 1kΩ
1111 X 01011 DAC C Output is terminated with 100kΩ
1111 X 01100 DAC D DAC O/P, wake-up
1111 X 01101 DAC D Floating output
1111 X 01110 DAC D Output is terminated with 1kΩ
1111 X 01111 DAC D Output is terminated with 100kΩ
1111 X 10000 DAC A-D DAC O/P, wake-up
1111 X 10001 DAC A-D Floating output
1111 X 10010 DAC A-D Output is terminated with 1kΩ
1111 X 10011 DAC A-D Output is terminated with 100kΩ
Table 1. Power-Down Mode Control
X = Don’t Care
