CP82C59AZ Datasheet IS82C59AZ, IS82C59A-12Z, IS82C59AZX96 | P13-P15

FN2784.6

September 8, 2015

End of Interrupt (EOI)

The In-Service (IS) bit can be reset either automatically

following the trailing edge of the last in sequence INTA pulse

(when AEOI bit in lCW1 is set) or by a command word that

must be issued to the 82C59A before returning from a

service routine (EOI Command). An EOI command must be

issued twice if servicing a slave in the Cascade mode, once

for the master and once for the corresponding slave.

There are two forms of EOl command: Specific and Non-

Specific. When the 82C59A is operated in modes which

preserve the fully nested structure, it can determine which IS

bit to reset on EOI. When a Non-Specific command is issued

the 82C59A will automatically reset the highest IS bit of

those that are set, since in the fully nested mode the highest

IS level was necessarily the last level acknowledged and

serviced. A non-specific EOI can be issued with OCW2

(EOl = 1, SL = 0, R = 0).

When a mode is used which may disturb the fully nested

structure, the 82C59A may no longer be able to determine

the last level acknowledged. In this case a Specific End of

Interrupt must be issued which includes as part of the

command the IS level to be reset. A specific EOl can be

issued with OCW2 (EOI = 1, SL = 1, R = 0, and L0 - L2 is the

binary level of the IS bit to be reset).

An lRR bit that is masked by an lMR bit will not be cleared by

a non-specific EOI if the 82C59A is in the Special Mask

Mode.

Automatic End of Interrupt (AEOI) Mode

If AEOI = 1 in lCW4, then the 82C59A will operate in AEOl

mode continuously until reprogrammed by lCW4. In this

mode the 82C59A will automatically perform a non-specific

EOI operation at the trailing edge of the last interrupt

acknowledge pulse (third pulse in 8080/85, second in

80C86/88/286). Note that from a system standpoint, this

mode should be used only when a nested multilevel interrupt

structure is not required within a single 82C59A.

Automatic Rotation (Equal Priority Devices)

In some applications there are a number of interrupting

devices of equal priority. In this mode a device, after being

serviced, receives the lowest priority, so a device requesting

an interrupt will have to wait, in the worst case until each of 7

other devices are serviced at most once. For example, if the

priority and “in service” status is:

Before Rotate (lR4 the highest priority requiring service)

After Rotate (lR4 was serviced, all other priorities rotated

correspondingly)

There are two ways to accomplish Automatic Rotation using

OCW2, the Rotation on Non-Specific EOI Command (R = 1,

SL = 0, EOI = 1) and the Rotate in Automatic EOI Mode

which is set by (R = 1, SL = 0, EOI = 0) and cleared by

(R = 0, SL = 0, EOl = 0).

Specific Rotation (Specific Priority)

The programmer can change priorities by programming the

lowest priority and thus, fixing all other priorities; i.e., if IR5 is

programmed as the lowest priority device, then IR6 will have

the highest one.

The Set Priority command is issued in OCW2 where: R = 1,

SL = 1, L0 - L2 is the binary priority level code of the lowest

priority device.

Observe that in this mode internal status is updated by soft-

ware control during OCW2. However, it is independent of the

End of Interrupt (EOI) command (also executed by OCW2).

Priority changes can be executed during an EOI command

by using the Rotate on Specific EOl command in OCW2

(R = 1, SL = 1, EOI = 1, and L0 - L2 = IR level to receive

lowest priority).

Interrupt Masks

Each Interrupt Request input can be masked individually by

the Interrupt Mask Register (IMR) programmed through

OCW1. Each bit in the lMR masks one interrupt channel if it

is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth.

Masking an IR channel does not affect the operation of other

channels.

Special Mask Mode

Some applications may require an interrupt service routine

to dynamically alter the system priority structure during its

execution under software control. For example, the routine

may wish to inhibit lower priority requests for a portion of its

execution but enable some of them for another portion.

IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

“IS” Status01010000

Priority

Status

76543210

lowest highest

IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

“IS” Status01000000

Priority

Status

21076543

highest lowest

82C59A

FN2784.6

September 8, 2015

The difficulty here is that if an Interrupt Request is

acknowledged and an End of Interrupt command did not

reset its IS bit (i.e., while executing a service routine), the

82C59A would have inhibited all lower priority requests with

no easy way for the routine to enable them.

That is where the Special Mask Mode comes in. In the

Special Mask Mode, when a mask bit is set in OCW1, it

inhibits further interrupts at that level and enables interrupts

from all other levels (lower as well as higher) that are not

masked.

Thus, any interrupts may be selectively enabled by loading

the mask register.

The Special Mask Mode is set by OCW3 where: ESMM = 1,

SMM = 1, and cleared where ESMM = 1, SMM = 0.

Poll Command

In this mode, the INT output is not used or the

microprocessor internal Interrupt Enable flip flop is reset,

disabling its interrupt input. Service to devices is achieved by

software using a Poll command.

The Poll command is issued by setting P = 1 in OCW3. The

82C59A treats the next RD

pulse to the 82C59A (i.e., RD =

0, CS

= 0) as an interrupt acknowledge, sets the appropriate

IS bit if there is a request, and reads the priority level.

Interrupt is frozen from WR

to RD.

The word enabled onto the data bus during RD

is:

W0 - W2: Binary code of the highest priority level request-

ing service.

I: Equal to a “1” if there is an interrupt.

This mode is useful if there is a routine command common to

several levels so that the INTA

sequence is not needed

(saves ROM space). Another application is to use the poll

mode to expand the number of priority levels to more than 64.

D7 D6 D5 D4 D3 D2 D1 D0

I----W2W1W0

EDGE

SENSE

LATCH

LTIM BIT

0 = EDGE

1 = LEVEL

8080/85

MODE

80C86/

88/286

MODE

INTA

FREEZE

INTA

FREEZE

FREEZE READ

IRR

WRITE

MASK

READ IMR

READ ISR

MASTER CLEAR

MASK LATCH

REQUEST

LATCH

IN - SERVICE

LATCH

NON-

MASKED

REQ

CLR

SET

TO OTHER PRIORITY CELLS

PRIORITY

RESOLVER

CONTROL

LOGIC

SET ISR

CLR ISR

ISR BIT

CLR

SET

NOTES:

1. Master clear active only during ICW1.

2. FREEZE

is active during INTA and poll sequence only.

3. Truth Table for D-latch.

C D Q Operation

1D1D1Follow

0XQn-1Hold

82C59A82C59A

FN2784.6

September 8, 2015

Reading the 82C59A Status

The input status of several internal registers can be read to

update the user information on the system. The following

registers can be read via OCW3 (lRR and ISR) or OCW1

(lMR).

Interrupt Request Register (IRR): 8-bit register which

contains the levels requesting an interrupt to be

acknowledged. The highest request level is reset from the

lRR when an interrupt is acknowledged. lRR is not affected

by lMR.

In-Service Register (ISR): 8-bit register which contains the

priority levels that are being serviced. The ISR is updated

when an End of Interrupt Command is issued.

Interrupt Mask Register: 8-bit register which contains the

interrupt request lines which are masked.

The lRR can be read when, prior to the RD

pulse, a Read

The ISR can be read when, prior to the RD

pulse, a Read

There is no need to write an OCW3 before every status read

operation, as long as the status read corresponds with the

previous one: i.e., the 82C59A “remembers” whether the lRR

or ISR has been previously selected by the OCW3. This is

not true when poll is used. In the poll mode, the 82C59A

treats the RD

following a “poll write” operation as an INTA.

After initialization, the 82C59A is set to lRR.

For reading the lMR, no OCW3 is needed. The output data bus

will contain the lMR whenever RD

is active and A0 = 1 (OCW1).

Polling overrides status read when P = 1, RR = 1 in OCW3.

Edge and Level Triggered Modes

This mode is programmed using bit 3 in lCW1.

If LTlM = “0”, an interrupt request will be recognized by a low to

high transition on an IR input. The IR input can remain high

without generating another interrupt.

If LTIM = “1”, an interrupt request will be recognized by a “high”

level on an IR input, and there is no need for an edge detection.

The interrupt request must be removed before the EOI

command is issued or the CPU interrupt is enabled to prevent a

second interrupt from occurring.

The priority cell diagram shows a conceptual circuit of the level

sensitive and edge sensitive input circuitry of the 82C59A. Be

sure to note that the request latch is a transparent D type latch.

In both the edge and level triggered modes the IR inputs

must remain high until after the falling edge of the first INTA

If the IR input goes low before this time a DEFAULT lR7 will

occur when the CPU acknowledges the interrupt. This can

be a useful safeguard for detecting interrupts caused by

spurious noise glitches on the IR inputs. To implement this

feature the lR7 routine is used for “clean up” simply

executing a return instruction, thus, ignoring the interrupt. If

lR7 is needed for other purposes a default lR7 can still be

detected by reading the ISR. A normal lR7 interrupt will set

the corresponding ISR bit, a default IR7 won’t. If a default

IR7 routine occurs during a normal lR7 routine, however, the

ISR will remain set. In this case it is necessary to keep track

of whether or not the IR7 routine was previously entered. If

another lR7 occurs it is a default.

In power sensitive applications, it is advisable to place the

82C59A in the edge-triggered mode with the IR lines

normally high. This will minimize the current through the

internal pull-up resistors on the IR pins.

LATCH

ARM

(NOTE 1)

EARLIEST IR

CAN BE

REMOVED

LATCH

ARM

(NOTE 1)

8080/85

LATCH

ARM

(NOTE 1)

80C86/88/286

8080/85

INT

INTA

NOTE:

1. Edge triggered mode only.

FIGURE 10. IR TRIGGERING TIMING REQUIREMENTS

82C59A82C59A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

CP82C59AZ

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

Interface - Specialized W/ANNEAL PERIPH INT CNTRLR 5V 8MHZ COM

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CP82C59AZ

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