CP82C59AZ Datasheet IS82C59AZ, IS82C59A-12Z, IS82C59AZX96 | P7-P9

FN2784.6

September 8, 2015

These events occur in an 8080/8085 system:

1. One or more of the INTERRUPT REQUEST lines

(IR0 - IR7) are raised high, setting the corresponding IRR

bit(s).

2. The 82C59A evaluates those requests in the priority

resolver and sends an interrupt (INT) to the CPU, if

appropriate.

3. The CPU acknowledges the lNT and responds with an

INTA

pulse.

4. Upon receiving an lNTA

from the CPU group, the highest

priority lSR bit is set, and the corresponding lRR bit is

reset. The 82C59A will also release a CALL instruction

code (11001101) onto the 8-bit data bus through D0 - D7.

5. This CALL instruction will initiate two additional INTA

pulses to be sent to 82C59A from the CPU group.

6. These two INTA

pulses allow the 82C59A to release its

preprogrammed subroutine address onto the data bus.

The lower 8-bit address is released at the first INTA

pulse

and the higher 8-bit address is released at the second

INTA

pulse.

7. This completes the 3-byte CALL instruction released by

the 82C59A. In the AEOI mode, the lSR bit is reset at the

end of the third INTA

pulse. Otherwise, the lSR bit

remains set until an appropriate EOI command is issued

at the end of the interrupt sequence.

The events occurring in an 80C86/88/286 system are the

same until step 4.

4. The 82C59A does not drive the data bus during the first

INTA

pulse.

5. The 80C86/88/286 CPU will initiate a second INTA

pulse.

During this INTA pulse, the appropriate ISR bit is set and

the corresponding bit in the IRR is reset. The 82C59A

outputs the 8-bit pointer onto the data bus to be read by

the CPU.

6. This completes the interrupt cycle. In the AEOI mode, the

ISR bit is reset at the end of the second INTA pulse. Oth-

erwise, the ISR bit remains set until an appropriate EOI

command is issued at the end of the interrupt subroutine.

If no interrupt request is present at step 4 of either sequence

(i.e., the request was too short in duration), the 82C59A will

issue an interrupt level 7. If a slave is programmed on IR bit

7, the CAS lines remain inactive and vector addresses are

output from the master 82C59A.

Interrupt Sequence Outputs

8080, 8085 Interrupt Response Mode

This sequence is timed by three INTA

pulses. During the first

lNTA

pulse, the CALL opcode is enabled onto the data bus.

First Interrupt Vector Byte Data: Hex CD

During the second INTA

pulse, the lower address of the

appropriate service routine is enabled onto the data bus.

ADDRESS BUS (16)

CONTROL BUS

DATA BUS (8)

I/OR I/OW INT INTA

CASCADE

LINES

CAS 0

CAS 1

CAS 2

/EN

CS RD WR INTAINTD

- D

SLAVE PROGRAM/

ENABLE BUFFER

INTERRUPT

REQUESTS

82C59A

IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ

FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE

D7 D6 D5 D4 D3 D2 D1 D0

Call Code11001101

82C59A82C59A

FN2784.6

September 8, 2015

When interval = 4 bits, A5 - A7 are programmed, while

A0 - A4 are automatically inserted by the 82C59A. When

interval = 8, only A6 and A7 are programmed, while A0 - A5

are automatically inserted.

During the third INTA

pulse, the higher address of the

appropriate service routine, which was programmed as byte 2

of the initialization sequence (A8 - A15), is enabled onto the

bus.

80C86, 8OC88, 80C286 Interrupt Response Mode

80C86/88/286 mode is similar to 8080/85 mode except that

only two Interrupt Acknowledge cycles are issued by the

processor and no CALL opcode is sent to the processor. The

first interrupt acknowledge cycle is similar to that of 8080/85

systems in that the 82C59A uses it to internally freeze the

state of the interrupts for priority resolution and, as a master,

it issues the interrupt code on the cascade lines. On this first

cycle, it does not issue any data to the processor and leaves

its data bus buffers disabled. On the second interrupt

acknowledge cycle in the 86/88/286 mode, the master (or

slave if so programmed) will send a byte of data to the

processor with the acknowledged interrupt code composed

as follows (note the state of the ADI mode control is ignored

and A5 - A11 are unused in the 86/88/286 mode).

Programming the 82C59A

The 82C59A accepts two types of command words

generated by the CPU:

1. Initialization Command Words (ICWs): Before normal

operation can begin, each 82C59A in the system must be

brought to a starting point - by a sequence of 2 to 4 bytes

timed by WR

pulses.

2. Operation Command Words (OCWs): These are the

command words which command the 82C59A to operate

in various interrupt modes. Among these modes are:

a. Fully nested mode.

b. Rotating priority mode.

c. Special mask mode.

d. Polled mode.

The OCWs can be written into the 82C59A anytime after

initialization.

Initialization Command Words (lCWs)

General

Whenever a command is issued with A0 = 0 and D4 = 1, this

is interpreted as Initialization Command Word 1 (lCW1).

lCW1 starts the initialization sequence during which the

following automatically occur:

a. The edge sense circuit is reset, which means that follow-

ing initialization, an interrupt request (IR) input must make

a low-to-high transition to generate an interrupt.

b. The Interrupt Mask Register is cleared.

c. lR7 input is assigned priority 7.

d. Special Mask Mode is cleared and Status Read is set to

lRR.

CONTENT OF SECOND INTERRUPT VECTOR BYTE

IR INTERVAL = 4

D7 D6 D5 D4 D3 D2 D1 D0

7A7A6A511100

6A7A6A511000

5A7A6A510100

4A7A6A510000

3A7A6A501100

2A7A6A501000

1A7A6A500100

0A7A6A500000

IR INTERVAL = 8

D7 D6 DS D4 D3 D2 D1 D0

7A7A6111000

6A7A6110000

5A7A6101000

4A7A6100000

3A7A6011000

2A7A6010000

1A7A6001000

0A7A6000000

CONTENT OF THIRD INTERRUPT VECTOR BYTE

D7 D6 D5 D4 D3 D2 D1 D0

A15 A14 A13 A12 A11 A10 A9 A8

CONTENT OF INTERRUPT VECTOR BYTE FOR

80C86/88/286 SYSTEM MODE

D7 D6 D5 D4 D3 D2 D1 D0

lR7T7T6T5T4T3 1 1 1

lR6T7T6T5T4T3 1 1 0

IR5T7T6T5T4T3 1 0 1

IR4T7T6T5T4T3 1 0 0

IR3T7T6T5T4T3 0 1 1

IR2T7T6T5T4T3 0 1 0

IR1T7T6T5T4T3 0 0 1

IR0T7T6T5T4T3 0 0 0

82C59A82C59A

FN2784.6

September 8, 2015

e. If lC4 = 0, then all functions selected in lCW4 are set to

zero. (Non-Buffered mode (see note), no Auto-EOI,

8080/85 system).

NOTE: Master/Slave in ICW4 is only used in the buffered mode.

Initialization Command Words 1 and 2 (ICW1, lCW2)

A5 - A15: Page starting address of service routines. In an

8080/85 system the 8 request levels will generate CALLS to

8 locations equally spaced in memory. These can be

programmed to be spaced at intervals of 4 or 8 memory

locations, thus, the 8 routines will occupy a page of 32 or 64

bytes, respectively.

The address format is 2 bytes long (A0 - A15). When the

routine interval is 4, A0 - A4 are automatically inserted by the

82C59A, while A5 - A15 are programmed externally. When

the routine interval is 8, A0 - A5 are automatically inserted by

the 82C59A while A6 - A15 are programmed externally.

The 8-byte interval will maintain compatibility with current

software, while the 4-byte interval is best for a compact jump

table.

In an 80C86/88/286 system, A15 - A11 are inserted in the

five most significant bits of the vectoring byte and the

82C59A sets the three least significant bits according to the

interrupt level. A10 - A5 are ignored and ADI (Address

interval) has no effect.

LTlM: If LTlM = 1, then the 82C59A will operate in the level

interrupt mode. Edge detect logic on the interrupt

inputs will be disabled.

ADI: ALL address interval. ADI = 1 then interval = 4; ADI

= 0 then interval = 8.

SNGL: Single. Means that this is the only 82C59A in the

system. If SNGL = 1, no ICW3 will be issued.

IC4: If this bit is set - lCW4 has to be issued. If lCW4 is

not needed, set lC4 = 0.

Initialization Command Word 3 (ICW3)

This word is read only when there is more than one 82C59A

in the system and cascading is used, in which case

SNGL = 0. It will load the 8-bit slave register. The functions of

this register are:

a. In the master mode (either when SP

= 1, or in buffered

mode when M/S = 1 in lCW4) a “1” is set for each slave in

the bit corresponding to the appropriate IR line for the

slave. The master then will release byte 1 of the call

sequence (for 8080/85 system) and will enable the corre-

sponding slave to release bytes 2 and 3 (for 80C86/88/

286, only byte 2) through the cascade lines.

b. In the slave mode (either when SP

= 0, or if BUF = 1 and

M/S = 0 in lCW4), bits 2 - 0 identify the slave. The slave

compares its cascade input with these bits and if they are

equal, bytes 2 and 3 of the call sequence (or just byte 2 for

80C86/88/286) are released by it on the Data Bus.

NOTE: (The slave address must correspond to the IR line it is

connected to in the master ID).

Initialization Command Word 4 (ICW4)

SFNM: If SFNM = 1, the special fully nested mode is pro-

grammed.

BUF: If BUF = 1, the buffered mode is programmed. In

buffered mode, SP/EN becomes an enable output

and the master/slave determination is by M/S.

M/S: If buffered mode is selected: M/S = 1 means the

82C59A is programmed to be a master, M/S = 0

means the 82C59A is programmed to be a slave. If

BUF = 0, M/S has no function.

AEOI: If AEOI = 1, the automatic end of interrupt mode is

programmed.

PM: Microprocessor mode: PM = 0 sets the 82C59A for

8080/85 system operation, PM = 1 sets the

82C59A for 80C86/88/286 system operation.

ICW1

ICW2

CASCADE

MODE

ICW3

IS ICW4

NEEDED

ICW4

READY TO ACCEPT

INTERRUPT REQUESTS

NO (SNGL = 1)

YES (SNGL = 0))

YES (IC4 = 1)

NO (IC4 = 0)

FIGURE 6. 82C59A INITIALIZATION SEQUENCE

82C59A82C59A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

CP82C59AZ

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Interface - Specialized W/ANNEAL PERIPH INT CNTRLR 5V 8MHZ COM

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CP82C59AZ

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