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DAC1401D125-DB
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P25
DAC1401D125 3
© IDT 2012. All rights r
eserved.
Product data sheet
Rev
. 03 — 2 July 2012
10 o
f 25
Integrated Device T
echnology
DAC1401D125
Dual 14-bit
DAC, up to 125
Msp
s
f
s
= 78 Msps; f
c
= 9.44 MHz, f
c
= 10.44 MHz;
=0d
B
F
S
Fig 5.
2
-tone SFDR
f
s
= 52 Msps; f
c
= 6.25 MHz, f
c
= 6.75 MHz; f
c
=7
.
2
5
M
H
z
,
f
c
= 7.75 MHz;
=0d
B
F
S
Fig 6.
4
-tone SFDR
f (MHz)
0
40
30
20
10
001aai988
−
60
−
40
−
80
−
20
0
α
(dBm)
−
100
f (MHz)
0
30
20
10
001aai989
−
60
−
40
−
80
−
20
0
α
(dBm)
−
100
DAC1401D125 3
© IDT 2012. All rights r
eserved.
Product data sheet
Rev
. 03 — 2 July 2012
1
1 of 25
Integrated Device T
echnology
DAC1401D125
Dual 14-bit
DAC, up to 125
Msp
s
f
s
= 78 Msps; from f
c
= 9.5 MHz, 1
10 kHz spacing;
=0d
B
F
S
Fig 7.
8
-tone SFDR
Fig 8.
INL as a function of the input code
f (MHz)
0
40
30
20
10
001aai990
−
60
−
40
−
80
−
20
0
α
(dBm)
−
100
001aaj004
0
−
2
2
4
INL
(dB)
−
4
input code
0
14500
11600
17400
8700
2900
5800
DAC1401D125 3
© IDT 2012. All rights r
eserved.
Product data sheet
Rev
. 03 — 2 July 2012
12 o
f 25
Integrated Device T
echnology
DAC1401D125
Dual 14-bit
DAC, up to 125
Msp
s
Fig 9.
DNL as a function of the in
put code
(1)
f
o
=0d
B
F
S
(2)
f
o
=
6d
B
F
S
(3)
f
o
=
12 dBFS
Fig 10.
SFDR full-scale
at 78 Msps as
a function of the output frequency
001aaj003
0
−
0.4
0.4
0.8
DNL
(dB)
−
0.8
input code
0
14820
11856
17784
8892
2964
5928
f
o
(MHz)
0
20
15
10
5
001aaj035
85
SFDR
(dBc)
60
65
70
75
80
(1)
(2)
(3)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P25
DAC1401D125-DB
Mfr. #:
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Description:
BOARD DEMO FOR DAC1401D125
Lifecycle:
New from this manufacturer.
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