DAC1401D125 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 13 of 25
Integrated Device Technology
DAC1401D125
Dual 14-bit DAC, up to 125 Msps
(1) f
o
=0dBFS
(2) f
o
= 6dBFS
(3) f
o
= 12 dBFS
Fig 11. SFDR full-scale at 125 Msps as a function of the output frequency
(1) f
s
= 125 Msps
(2) f
s
= 100 Msps
(3) f
s
=78Msps
(4) f
s
=52Msps
Fig 12. Digital supply current as a function of f
o
/f
s
f
o
(MHz)
0 2515 20105
001aaj038
85
SFDR
(dBc)
60
65
70
75
80
(1)
(2)
(3)
f
o
/f
s
0 0.50.30.20.1
001aai938
8
4
12
16
I
DDD
(mA)
0
0.4
(1)
(2)
(3)
(4)
DAC1401D125 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 14 of 25
Integrated Device Technology
DAC1401D125
Dual 14-bit DAC, up to 125 Msps
10. Application information
10.1 General description
The DAC1401D125 is a dual 14-bit DAC operating up to 125 Msps. Each DAC consists of
a segmented architecture, comprising a 7-bit thermometer sub-DAC and a 7-bit binary
weighted sub-DAC.
Two modes are available for the digital input depending on the status of the pin MODE. In
Dual port mode, each DAC uses its own data input line at the same frequency as the
update rate. In Interleaved mode, both DACs use the same data input line at twice the
update rate.
Each DAC generates on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN two complementary
current outputs. This provides a full-scale output current (I
O(fs)
), up to 20 mA. A single
common or two independent full-scale current controls can be selected for both channels
using pin GAINCTRL. An internal reference is available for the reference current which is
externally adjustable using pin REFIO.
The DAC1401D125 operates at 3.3 V and has separate digital and analog power
supplies. Pin PWD is used to power-down the device. The digital input is 1.8 V compliant,
3.3 V compliant and 5 V tolerant.
10.2 Input data
The DAC1401D125 input follows a straight binary coding where DA13 and DB13 are the
Most Significant Bits (MSB) and DA0 and DB0 are the Least Significant Bits (LSB).
The setting applied to pin MODE defines whether the DAC1401D125 operates in Dual
port mode or in Interleaved mode (see Table 6).
Fig 13. Analog supply current as a function of the output current
001aaj032
l
O
(mA)
0 2015105
20
40
60
I
DDA
(mA)
0
DAC1401D125 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 15 of 25
Integrated Device Technology
DAC1401D125
Dual 14-bit DAC, up to 125 Msps
10.2.1 Dual port mode
The data and clock circuit for Dual port mode operation is shown in Figure 14.
Each DAC has its own independent data and clock inputs. The data enters the input latch
on the rising edge of the WRTA/WRTB signal and is transferred to the DAC latch. The
output is updated on the rising edge of the CLKA/CLKB signal.
Table 6. Mode selection
Mode Function DA13 to DA0 DB13 to DB0 Pin 17 Pin 18 Pin 19 Pin 20
0 Interleaved mode active off IQWRT IQCLK IQRESET IQSEL
1 Dual port mode active active WRTA CLKA CLKB WRTB
Fig 14. Dual port mode operation
Fig 15. Dual port mode timing
14
14
001aai823
DA13 to DA0
WRTA
WRTB
CLKA
CLKB
INPUT A
LATCH
DAC A
LATCH
14
14
DB13 to DB0
INPUT B
LATCH
DAC B
LATCH
001aai939
DA13 to DA0/
DB13 to DB0
N N+1
N2N1 N N+1 N+2
N+2
N+3
WRTA/
WRTB
CLKA/
CLKB
IOUTAP, IOUTAN/
IOUTBP, IOUTBN

DAC1401D125-DB

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BOARD DEMO FOR DAC1401D125
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