14
LT4220
4220f
APPLICATIO S I FOR ATIO
WUUU
Supply Tracking
If the TRACK pin (Pin 7) is high the supply power-up
tracking mode is enabled. This feature forces both sup-
plies to reach their final value at the same time, during
power-up and for faults that drive the output supplies to
zero. During this mode the GATE pins are controlled to
keep the differential magnitude of the FB pins to within
50mV. The FB pins are scaled versions of the output
voltages. Therefore, control of the FB pins, via the GATE
pins, will control the output voltages at the same scale.
|∆V
FB(TRK)
| = |V
FB
+
– V
FB
–
| (6)
Supply tracking will continue until: either FB pin reaches
the associated PWRGD threshold. If any fault condition
occurs that turns the GATE pins off, supply tracking will be
reenabled. The GATE off conditions include: (1) either ON
pin detects undervoltage, (2) internal undervoltage lock-
out, (3) the fault latch is set by a current limit time-out.
V
EE
Bypassing
The V
EE
supply pin should be filtered with an RC network
to reduce high dV/dt slew rates from disturbing internal
circuits. Typical RC bypassing sufficient to prevent circuit
misbehavior is R14 = 10Ω and C5 = 1µF. The GATE
–
,
SENSEK and SENSE
–
pins have been designed such that
they can be pulled below or above V
EE
for short periods of
time while the V
EE
pin is reaching its steady state voltage.
If desired, a higher R14 • C5 time constant may be used to
prevent short circuit transients from tripping the V
EE
undervoltage lockout circuit at –2.45V. R14 should be
sufficient to decouple C5 from causing transients on V
IN–
during live insertion.
Under the condition of a short circuit on V
OUT
–, parasitic
inductance and resistance in the V
IN
– path will cause V
IN
–
to collapse toward 0V causing the V
EE
pin voltage to also
discharge toward 0V before the external FET can be turned
off (typically 7µs to 10µs). To prevent a UVLO condition
from occurring, the R14 • C5 time constant should be
sufficient to hold the V
EE
pin voltage out of the V
EE
UVLO
voltage range. If the V
EE
pin reaches its UVLO voltage,
GATE
+
will also be pulled low. For the case where C3 is
large, causing an even slower N-channel FET turnoff,
higher RC bypassing may be necessary to prevent tripping
the V
EE
UVLO.
ON
+
, ON
–
Bypass Capacitors
Bypass capacitors are required from ON
+
to ground and
ON
–
to ground. A typical time constant is:
TC (ON
+
) = (R1||R2)C7 = 44µs
TC (ON
–
) = (R3||R4)C8 = 44µs
Supply Ringing
Normal circuit design practice calls for capacitive bypass-
ing of the input supply to active devices. The opposite is
true for Hot Swap circuits that are connected into a
backplane, where capacitive loading would cause tran-
sients during an abrupt connection to the backplane. With
little or no capacitive decoupling on the powered side of
the N-channel FETs, connection transients or load tran-
sients will typically cause ringing on the supply leads due
to parasitic inductance. It is recommended to use a
snubber circuit comprising of a series 10Ω and 0.1µF
capacitor to dampen transient ringing. The supply
decoupling circuit on the V
EE
pin also provides a snubber
for V
IN
–.
Additionally, if the supply voltage overshoot can exceed
the ±22V maximum rating on the part, a transient voltage
suppressor is recommended. Voltage transients can oc-
cur during load short-circuit conditions, where parasitic
inductance in the supply leads can build up energy before
the external N-channel FET can be turned off. This is
especially true for the negative side FET where a large C3
value slows the turn off of the N-channel FET. Subsequent
overshoot when the FET is finally turned off can be as
much as 2× the supply voltage even with the snubber
circuit. Additional protection using a transient suppressor
may be needed to prevent exceeding the maximum supply
voltage rating.
Supply Reversal Protection
A variety of conditions on V
OUT
+ and V
OUT
– may result in
supply reversal. To protect devices connected to V
OUT
+
and V
OUT
– protection diodes should be used. 1N4001
diodes can be used for most aplications. Connection of
these diodes (D1, D2) are shown in the front page Typical
Application.
