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LT4220CGN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
7
LT4220
4220f
UU
U
PI FU CTIO S
V
EE
(Pin 1): Negative Supply. The negative supply input
ranges from –2.7V to –16.5V for normal operation. I
EE
is
typically –1.6mA. An internal undervoltage lockout circuit
disables the device for inputs greater than –2.45V. A 10Ω,
1µF RC bypass network from V
IN
– to the V
EE
pin decouples
transients from the device.
SENSEK (Pin 2): Negative Supply Current Limit Kelvin
Sense Pin. Connect to V
IN
–.
SENSE
–
(Pin 3): Negative Supply Current Limit Sense Pin.
A sense resistor is placed in the supply path between
SENSEK and SENSE
–
. The current limit circuit will regulate
the voltage across the sense resistor to
–50mV (SENSEK – SENSE
–
) when the FB
–
voltage is less
than –0.7V. If V
FB
–
goes above –0.7V, the voltage across
the sense resistor decreases linearly and stops at –15mV
when V
FB
–
is 0V. If current limit is not used, connect to
SENSEK.
GATE
–
(Pin 4): Gate Drive for the External Negative Supply
N-Channel FET. An internal 10µA current source drives the
pin. An external capacitor connected from the GATE
–
pin
to V
OUT
– will control the rising slope of the V
OUT
– signal.
The voltage is clamped to 9V above V
EE
.
When the current limit is reached, the GATE
–
pin voltage
will be adjusted to maintain a constant voltage across the
R
S
–
resistor while the timer capacitor starts to charge. If
the TIMER pin voltage exceeds 1.24V, the fault latch will be
set and both GATE
–
and GATE
+
pins will be pulled low.
The GATE
–
pin is pulled to V
EE
whenever the ON
+
pin is
below 1.24V, the ON
–
pin is above –1.24V, or either supply
is in the undervoltage lockout voltage range, or the fault
latch is set by the TIMER pin rising above 1.24V.
FB
–
(Pin 5): Negative Power Good Comparator Input. This
pin monitors the negative output voltage (V
OUT
–) with an
external resistive divider. When the voltage on FB
–
is
below –1.24V and the initial GATE
–
drive voltage has
reached a maximum (indicated by setting the internal
GATE
–
good latch) and the FB
+
release conditions are met,
the PWRGD pin is released. PWRGD is pulled low when the
FB
–
pin is above –1.185V. Note the PWRGD pin is wire-
ORed with the FB
+
pin conditions.
FB
–
also controls the negative supply current limit sense
amplifier input offset to provide foldback current limit. The
FB
–
pin linearly reduces the negative supply sense ampli-
fier offset from –52mV to –15mV for FB
–
in the range
–0.75V < FB
–
< 0V. To disable V
EE
PWRGD and foldback
current limit, the FB
–
pin should be set to a voltage in the
range: –1.3V > FB
–
> V
EE
+ 0.5V but should never be more
negative then –5.8V for normal operation.
ON
–
(Pin 6): The Negative Supply Good Comparator Input.
This pin monitors the negative input voltage (V
EE
) with an
external resistive divider for undervoltage lockout. When
the voltage at the ON
–
pin is below the V
ON
–
H
high-to-low
threshold (–1.24V), the negative supply is considered
good. If the ON
–
pin rises above –1.185V, both GATE
–
and
GATE
+
are pulled low. If ON
–
is not used, the ON
–
pin
should be set to –1.3V > ON
–
> V
EE
+ 0.5V.
TRACK (Pin 7): Supply Tracking Mode Control. If the TRACK
pin is pulled high, the internal supply tracking circuit will
be enabled during start-up. The TRACK circuit monitors
the FB
+
and the FB
–
pins to keep their magnitude within a
small voltage range by controlling the GATE
+
and GATE
–
charge currents. The tracking is disabled when either FB
comparator indicates the output is good. Tracking is re-
enabled if ON
+
is pulled below 1.185V, ON
–
is pulled above
–1.185V or either supply is below the internal undervoltage
lockout. Typically, the TRACK pin is tied to GND or to V
CC
.
If left floating, tracking is enabled.
TIMER (Pin 8): Fault Time Out Control. An external timing
capacitor at this pin programs the maximum time the part
is allowed to remain in current limit before issuing a fault
and turning off the external FETs. Additionally, for
autorestart, this pin controls the time before an autorestart
is initiated.
When the part goes into current limit, a 65µA pull-up
current source starts to charge the timing capacitor. When
the voltage reaches V
TIMERH
(1.24V), the internal fault
latch is set, FAULT pulls low and both GATE pins are pulled
low; the pull-up current will be turned off and the capacitor
is discharged by a 3.3µA pull-down current. When the
TIMER pin falls below 0.5V, the part is allowed to restart
if the ON
+
pin is pulsed below 1.185V, thereby resetting
internal fault latch—typically done by connecting the
8
LT4220
4220f
UU
U
PI FU CTIO S
FAULT pin to the ON
+
pin, otherwise the part remains
latched off.
To disable the timeout circuit breaker, connect the TIMER
pin to GND.
GND (Pin 9): Supply Ground Pin.
PWRGD (Pin 10): Open-Collector Output to GND. PWRGD
goes to high impedance after the initial GATE
–
and final
GATE
+
pins
have reached their maximum voltage and after
the FB
+
pin goes above 1.24V low-to-high threshold and
after the FB
–
pin falls below –1.24V high-to-low threshold.
An external pull-up resistor can pull the pin to a voltage
higher or lower than V
CC
. If not used, PWRGD can be left
floating or tied to GND.
FAULT (Pin 11): Open-Collector Output to GND. The
FAULT pin is pulled low whenever the TIMER pin rises
above V
TIMERH
(1.24V) threshold, thereby setting the
internal fault latch. It goes to high impedance whenever the
internal fault latch is reset. The fault latch is reset with
either internal undervoltage lockout conditions, or by the
ON comparators if the TIMER pin is also below 0.5V. If not
used, the FAULT pin can be left floating or tied to GND.
ON
+
(Pin 12): Positive Supply Good Comparator Input. It
monitors the positive input voltage (V
CC
) with an external
resistive divider for undervoltage lockout. When the volt-
age on ON
+
is above the V
ON
+
H
high-to-low threshold
(1.24V) the positive supply is considered good. If ON
+
drops below 1.185V, both GATE
–
and GATE
+
are pulled
low.
If ON
+
is pulled low after a current limit fault and when the
TIMER pin is below 0.5V, the fault latch is reset allowing
the part to turn back on. Typically the FAULT pin is tied
back to the ON
+
pin for autorestart. If not used, the ON
+
pin
should be set to a voltage in the range of 1.3V < ON
+
< V
CC
+ 0.3V. The ON
+
pin requires a bypass capacitor connected
to ground.
FB
+
(Pin 13): Positive Power Good Comparator Input. This
pin monitors the positive output voltage (V
OUT
+) with an
external resistor divider. When the voltage on FB
+
is above
the V
FB
+
H
low-to-high threshold (1.24V) and the GATE
+
drive voltage has reached a maximum, the PWRGD is
released. PWRGD is pulled low when the FB
+
pin is below
1.185V. The PWRGD pin is wire-ORed with the FB
–
pin
conditions.
FB
+
also controls the positive current limit sense amplifier
input offset to provide foldback current limit. The FB
+
pin
linearly reduces the positive sense amplifier offset from
48mV to 15mV for FB
+
in the range 0.85V > FB
+
> 0V. If
PWRGD and foldback current limit are not used, the FB
+
pin should be set to a voltage in the range of 1.3V < FB
+
<
V
CC
+ 0.3V.
GATE
+
(Pin 14): High Side Gate Drive for the External
Positive Supply N-Channel FET. An internal charge pump
guarantees at least 3.5V above V
CC
, for supply voltages at
±2.7V increasing to a minimum of 5V above V
CC
for supply
voltages greater than ±5V. A 10µA pull-up current source
drives the pin. An external capacitor connected from the
GATE
+
pin to GND will control the rising slope of the GATE
+
signal. The voltage is clamped to 7V above V
CC
.
When the current limit is reached, the GATE
+
pin voltage
will be adjusted to maintain a constant voltage across the
R
S
+
resistor while the timer capacitor starts to charge. If
the TIMER pin voltage exceeds 1.24V, the GATE
+
pin will
be pulled low.
The GATE
+
pin is pulled to GND whenever the ON
+
pin is
below 1.24V, the ON
–
pin is above –1.24V, either supply is
in the undervoltage lockout voltage range, or the TIMER
pin rises above 1.24V.
SENSE
+
(Pin 15): Positive Supply Current Limit Sense Pin.
A sense resistor must be placed in the supply path be-
tween V
CC
and SENSE
+
. The current limit circuit will
regulate the voltage across the sense resistor to 50mV
(V
CC
– SENSE
+
) when the FB
+
voltage is greater than
0.85V. If V
FB
+
goes below 0.85V, the voltage across the
sense resistor decreases linearly and stops at 15mV when
V
FB
+
is 0V.
V
CC
(Pin 16): Positive Supply. The positive supply input
ranges from 2.7V to 16.5V for normal operation. I
CC
is
typically 2.7mA. An internal undervoltage lockout circuit
disables the chip for inputs less than 2.45V. Place a 0.1µF
bypass capacitor next to the V
CC
pin.
9
LT4220
4220f
BLOCK DIAGRA
W
–
+
13
–
+
1.24V
–
+
–1.24V
UVLO
V
CC
AND
V
EE
GOOD
FB
+
6
ON
–
–
+
–
+
–
+
–
+
1.24V
0.5V
1.24V
12
ON
+
FB
–
–1.24V
P GATE
GOOD
N GATE
GOOD
5
TRACK
7
V
EE
V
CC
V
CC
1
GND
9 16
S
R
Q
S
R
Q
S
R
Q
Q
Q
Q
S
R
R
Q
Q
10
PWRGD
GATE GOOD
LATCHES
TRACK OFF
LATCH
TOFF
GATE ON
V
CC
V
CC
FAULT
FAULT
LATCH
TIMER AND LOGIC
11
FAULT
GATE
+
15
SENSE
+
PUMP
I
LIM
V
CC
3µA
10µA
10µA
ON
ON
EN
TRACK
FB
+
60µA
CURRENT LIMIT
FROM SENSE AMPS
–
+
–
+
14
GATE
–
4
SENSEK
4220 BD
2
SENSE
–
3
8
TIMER
WEAK DIODES
SUBSTRATE
+
–
+
–
53mV
52mV
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LT4220CGN#PBF

Mfr. #:
Buy LT4220CGN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Dual Hot Swap Controller Pos/Neg
Lifecycle:
New from this manufacturer.
Delivery:
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