7
Recommended turn on sequence
Apply VDD1_TX and VDD2_TX
Apply VDD_RX
Apply VREF
Apply TRSW11,12,21 and 22
Apply ANTSW1 and ANTSW2
Apply PA_EN
For TX HPM Apply PAMOD HI
For TX LPM Apply PAMOD LO
For RX HG Apply LNA1,2 Mode HI
For RX LG Apply LNA1,2 Mode LO
Apply RF Input not to exceed 10 dBm
Turn o in reverse order
Notes:
VDD1_TX, VDD2_TX can be tied together to reduce supply voltages, but
VREF needs to be a regulated voltage which is optimized for 2.8 V at VDD
of 3.6 V.
PA_EN and PAMODE are CMOS compatible pin; however, this can be
driven with 3 V0 for logic high.
Use jumpers on eval board to set control signal for desired mode of
operation.
Figure 1. Pins on back of Demoboard
Evaluation Board Description
Table 6. Pin Description:
Top
Pin No. Function
Bottom
Pin No. Function
1 VDD2_TX 2 VDD2_Sense
3 VDD_RX 4 GND
5 VDD1_TX 6 GND
7 ANTSW1 8 GND
9 PAMODE 10 TRSW11
11 TRSW12 12 TRSW21
13 TRSW22 14 PA_EN
15 VREF 16 GND
17 LNA1_MODE 18 GND
19 LNA2_MODE 20 ANTSW2
Table 7. TX Typical Test Conditions:
TX ANT1
PIN HPM LPM Function
VDD1,2_TX 3.6 V 3.6 V Battery
PA_MODE 3.0 V 0 V Low Power Mode
VREF 2.8 V 2.8 V Bias Control
PA_EN 3.0 V 3.0 V PA Enable
ANTSW1,2 H L ANT Select
TRSW12,11,22,21 H L H L RX/TX Select
Table 8. RX Typical Test Conditions:
ANT1 RX1 ANT2 RX2
PIN HG LG Function
VDD_RX 3.3 V 3.3 V Battery
LNA1_MODE 3.0 V 0 V LNA1 Control
LNA2_MODE 3.0 V 0 V LNA2 Control
VREF 2.8 V 2.8 V Bias Control
ANTSW1,2 X X ANT Select
TRSW12,11,22,21 L H L H RX/TX Select
