IDT71V2559S85BG8 Datasheet IDT71V2559S80PF, IDT71V2559S75BG, IDT71V2559S75BG8 | P1-P3

OCTOBER 2000

DSC-4878/05

ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

Pin Description Summary

Features

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128K x 36, 256K x 18 memory configurations

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Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

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ZBT

Feature - No dead cycles between write and read

cycles

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Internally synchronized output buffer enable eliminates the

need to control OE

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Single R/W (READ/WRITE) control pin

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4-word burst capability (Interleaved or linear)

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Individual byte write (BW1 - BW4) control (May tie active)

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Three chip enables for simple depth expansion

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3.3V power supply (±5%)

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2.5V (±5%)I/O Supply (VDDQ)

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Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Description

The IDT71V2557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-

bit) synchronous SRAMs organized as 128K x 36 / 256K x 18. They are

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

given the name ZBT

, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock

cycle, and on the next clock cycle the associated data cycle occurs, be

it read or write.

-A

Address Inputs Input Synchronous

, CE

Chip Enables Input Synchronous

Output Enable Input Asynchronous

R/W Read/Write Signal Input Synchronous

CEN

Clock Enable Input Synchronous

, BW

Individual Byte Write Selects Input Synchronous

CLK Clock Input N/A

ADV/LD Advance burst address / Load new address Input Synchronous

LBO

Linear / Interleaved Burst Order Input Static

I/O

-I/O

, I/O

-I/O

Data Input / Output I/O Synchronous

, V

DDQ

Core Power, I/O Power Supply Static

Ground Supply Static

4878 tbl 01

The IDT71V2557/59 contain address, data-in and control signal

registers. The outputs are flow-through (no output data register). Output

enable is the only asynchronous signal and can be used to disable the

outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V2557/59

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

user to deselect the device when desired. If any one of these three is not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state one cycle after the chip is deselected or a write

is initiated.

The IDT71V2557/59 have an on-chip burst counter. In the burst

mode, the IDT71V2557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst

counter (ADV/LD = HIGH).

The IDT71V2557/59 SRAMs utilize IDT's latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball

grid array (BGA) and a 165 fine pitch ball grid array (fBGA).

IDT71V2557

IDT71V2559

128K x 36, 256K x 18,

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter,

Flow-Through Outputs

6.42

IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

-A

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the

rising edge of CLK, ADV/LD low, CEN low, and true chip enables.

ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address

and control when it is sampled low at the rising edge of clock with the chip selected. When

ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD

is sampled high then the internal burst counter is advanced for any burst that was in

progress. The external addresses are ignored when ADV/LD is sampled high.

R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a

Read or Write access to the memory array. The data bus activity for the current cycle takes

place one clock cycle later.

CEN

Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous

inputs, including clock are ignored and outputs remain unchanged. The effect of CEN

sampled high on the device outputs is as if the low to high clock transition did not occur.

For normal operation, CEN must be sampled low at rising edge of clock.

Individual Byte

Write Enables

I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.

On load write cycles (When R/

and ADV/

are sampled low) the appropriate byte write

signal (BW

-BW

) must be valid. The byte write signal must also be valid on each cycle of

a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate

byte(s) of data are written into the device one cycle later. BW

-BW

can all be tied low if

always doing write to the entire 36-bit word.

Chip Enables I LOW Synchronous active low chip enable. CE

and CE

are used with CE

to enable the

IDT71V2557/59. (

sampled high or CE

sampled low) and ADV/

low at the

rising edge of clock, initiates a deselect cycle. The ZBT

has a one cycle deselect, i.e.,

the data bus will tri-state one clock cycle after deselect is initiated.

Chip Enable I HIGH Synchronous active high chip enable. CE

is used with CE

and CE

to enable the chip.

has inverted polarity but otherwise identical to CE

and CE

CLK Clock I N/A This is the clock input to the IDT71V2557/59. Except for OE, all timing references for the

device are made with respect to the rising edge of CLK.

I/O

-I/O

I/O

-I/O

Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge

of CLK. The data output path is flow-through (no output register).

LBO

Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected.

When LBO is low the Linear burst sequence is selected. LBO is a static input, and it must

not change during device operation..

Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V2557/59. When OE

is HIGH the I/O pins are in a high-impedance state. OE does not need to be actively

controlled for read and write cycles. In normal operation, OE can be tied low.

Power Supply N/A N/A 3.3V core power supply.

DDQ

Power Supply N/A N/A 2.5V I/O Supply.

Ground N/A N/A Ground.

4878 tbl 02

6.42

IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with

ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram  128K x 36

Clk

Address A [0:16]

Control Logic

Address

Control

DI DO

Input R

egister

4878 drw 01

Clock

Data I/O [0:31], I/O P[1:4]

Mux

Sel

Gate

,CE

R/W

CEN

ADV/LD

LBO

128K x 36 BIT

MEMORY ARRAY

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

IDT71V2559S85BG8

Mfr. #:

Buy IDT71V2559S85BG8

Manufacturer:

Description:

IC SRAM 4.5M PARALLEL 119PBGA

Lifecycle:

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IDT71V2559S85BG8

IDT71V2559S85BG8

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