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IDT71V2559S85BG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
6.42
IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with
ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
7
Pin Configuration  128K x 36, 119 BGA
Pin Configuration  256K x 18, 119 BGA
Top View
Top View
NOTES:
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. J3 does not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
3. G4 and A4 are reserved for future 8M and 16M respectively.
4. DNU = Do not use; Pins U2, U3, U4, U5 and U6 are reserved for respective JTAG Pins: TMS, TDI, TCK, TDO and TRST on future revisions. Within this
current version, these pins are not connected.
5. On future revisions, Pin T7 will be used for ZZ (sleep mode).
1234567
A
V
DDQ
A
6
A
4
A
8
A
16
V
DDQ
B
NC CE
2
A
3
ADV/
LD
A
9
CE
2
NC
C
A
7
A
2
V
DD
A
12
A
15
NC
D
I/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
E
I/O
17
I/O
18
V
SS
V
SS
I/O
13
I/O
14
F
V
DDQ
I/O
19
V
SS
OE
V
SS
I/O
12
V
DDQ
G
I/O
20
I/O
21
BW
3
BW
2
I/O
11
I/O
10
H
I/O
22
I/O
23
V
SS
R/W
V
SS
I/O
9
I/O
8
J
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
K
I/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
L
I/O
25
I/O
27
BW
4
NC
BW
1
I/O
4
I/O
5
M
V
DDQ
I/O
28
V
SS
CEN
V
SS
I/O
3
V
DDQ
N
I/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
P
I/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
R
NC A
5
LBO
V
DD
A
13
T
NC NC A
10
A
11
A
14
NC NC
(5)
U
V
DDQ
DNU
(4)
DNU
(4)
DNU
(4)
DNU
(4)
DNU
(4)
V
DDQ
4878 drw 13A
V
SS(1)
NC
NC(3)
CE
1
NC(3)
V
DD(2)
V
SS(1)
,
NC
1234567
A
V
DDQ
A
6
A
4
NC(3)
A
8
A
16
V
DDQ
B
NC CE2 A
3
ADV/
LD
A
9
CE
2
NC
C
A
7
A
2
V
DD
A
13
A
17
NC
D
I/O
8
NC V
SS
NC V
SS
I/O
7
NC
E
NC I/O
9
V
SS
V
SS
NC I/O
6
F
V
DDQ
NC V
SS
OE
V
SS
I/O
5
V
DDQ
G
NC I/O
10
BW
2
NC I/O
4
H
I/O
11
NC V
SS
R/W
V
SS
I/O
3
NC
J
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
K
NC I/O
12
V
SS
CLK V
SS
NC I/O
2
L
I/O
13
NC NC
BW
1
I/O
1
NC
M
V
DDQ
I/O
14
V
SS
CEN
V
SS
NC V
DDQ
N
I/O
15
NC V
SS
A
1
V
SS
I/O
0
NC
P
NC I/O
P2
V
SS
A
0
V
SS
NC I/O
P1
R
NC A
5
LBO
V
DD
A
12
T
NC A
10
A
15
NC A
14
A
11
NC
(5)
U
V
DDQ
DNU
(4)
DNU
(4)
DNU
(4)
DNU
(4)
DNU
(4)
V
DDQ
4878 drw 13B
NC
SS(1)
V
V
SS
V
SS
CE
1
NC(3)
V
DD(2)
V
SS(1)
,
NC
6.42
8
IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Configuration  128K x 36, 165 fBGA
Pin Configuration - 256K x 18, 165 fBGA
NOTES:
1. H1 and N7 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. H2 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.
3. A9, B9, B11, A1, R2, and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively.
4. DNU = Do not use; Pins P5, P7, R5, R7 and N5 are reserved for respective JTAG Pins: TDI, TDO, TMS, TCK and TRST on future revisions. Within this
current version, these pins are not connected.
5. On future revisions, pin H11 will be used for ZZ (sleep mode).
1234567891011
ANC
(3)
A
7
CE
1
BW
3
BW
2
CE
2
CEN
ADV/LD NC
(3)
A
8
NC
BNC A
6
CE
2
BW
4
BW
1
CLK R/W
OE
NC
(3)
A
9
NC
(3)
CI/O
P3
NC V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P2
DI/O
17
I/O
16
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
15
I/O
14
EI/O
19
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
FI/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
11
I/O
10
GI/O
23
I/O
22
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
9
I/O
8
HV
SS
(1)
V
DD
(2)
NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC NC
(5)
JI/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
I/O
6
KI/O
27
I/O
26
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
I/O
4
LI/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
MI/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
NI/O
P4
NC V
DDQ
V
SS
DNU
(4)
NC V
SS
(1)
V
SS
V
DDQ
NC I/O
P1
PNCNC
(3)
A
5
A
2
DNU
(4)
A
1
DNU
(4)
A
10
A
13
A
14
NC
R
LBO
NC
(3)
A
4
A
3
DNU
(4)
A
0
DNU
(4)
A
11
A
12
A
15
A
16
4878 tbl 25
1234567891011
ANC
(3)
A
7
CE
1
BW
2
NC
CE
2
CEN
ADV/LD NC
(3)
A
8
A
10
BNC A
6
CE
2
NC
BW
1
CLK R/W
OE
NC
(3)
A
9
NC
(3)
CNC NCV
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P1
DNC I/O
8
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
7
ENC I/O
9
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
6
FNCI/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
5
GNC I/O
11
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
4
HVss
(1)
V
DD
(2)
NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC NC
(5)
JI/O
12
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
NC
KI/O
13
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
NC
LI/O
14
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
NC
MI/O
15
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
NC
NI/O
P2
NC V
DDQ
V
SS
DNU
(4)
NC V
SS
(1)
V
SS
V
DDQ
NC NC
PNC NC
(3)
A
5
A
2
DNU
(4)
A
1
DNU
(4)
A
11
A
14
A
15
NC
R
LBO
NC
(3)
A
4
A
3
DNU
(4)
A
0
DNU
(4)
A
12
A
13
A
16
A
17
4878 tbl 25a
6.42
IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V SynchronousSRAMs with
ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
9
Interleaved Burst Sequence Table (LBO=VDD)
Partial Truth Table for Writes
(1)
Synchronous Truth Table
(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
CEN
R/
W
CE
1
,
CE
2
(5)
ADV/
LD
BW
x
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
L L L L Valid External X LOAD WRITE D
(7)
L H L L X External X LOAD READ Q
(7)
L X X H Valid Internal LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)
(2)
D
(7)
L X X H X Internal LOAD READ /
BURST READ
BURST READ
(Advance burst counter)
(2)
Q
(7)
L X H L X X X DESELECT or STOP
(3)
HIZ
L X X H X X DESELECT / NOOP NOOP HIZ
H X X X X X X SUSPEND
(4)
Previous Value
4878 tbl 08
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
4878 tbl 10
OPERATION
R/
W
BW
1
BW
2
BW
3
(3)
BW
4
(3)
READ H X X X X
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2)
LLHHH
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2)
LHLHH
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
LHHLH
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
LHHHL
NO WRITE LHHHH
4878 tbl 09
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

IDT71V2559S85BG8

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Description:
IC SRAM 4.5M PARALLEL 119PBGA
Lifecycle:
New from this manufacturer.
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