DS2751
13 of 19
PORPOR Indicator bit. This bit is set to a 1 when the DS2751 experiences a power-on-reset (POR)
event. To use the POR bit to detect a power-on-reset, the POR bit must be set to a 0 by the host system
upon power-up and after each subsequent occurrence of a POR.
PIOPIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.
X—Reserved Bits.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-
Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2751
is a slave device. The bus master is typically a microprocessor in the host system. The discussion of this
bus system consists of four topics: 64-Bit Net Address, Hardware Configuration, Transaction Sequence,
and 1-Wire Signaling.
64-BIT NET ADDRESS
Each DS2751 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first 8
bits are the 1-Wire family code (51h for DS2751). The next 48 bits are a unique serial number. The last 8
bits are a CRC of the first 56 bits (see Figure 11). The 64-bit net address and the 1-Wire I/O circuitry built
into the device enable the DS2751 to communicate through the 1-Wire protocol detailed in the 1-Wire
Bus System section of this data sheet.
Figure 11. 1-WIRE NET ADDRESS FORMAT
8-Bit CRC 48-Bit Serial Number
8-Bit Family
Code (51h)
MSb LSb
CRC GENERATION
The DS2751 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure
error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of
the address and compare it to the CRC from the DS2751. The host system is responsible for verifying the
CRC value and taking action as a result. The DS2751 does not compare CRC values and does not prevent
a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result
in a communication channel with a very high level of integrity.
The CRC can be generated by the host using a circuit consisting of a Shift Register and XOR gates as
shown in Figure 12, or it can be generated in software. Additional information about the Dallas 1-Wire
CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with
Dallas Semiconductor Touch Memory Products.
In the circuit in Figure 12, the shift bits are initialized to 0. Then, starting with the least significant bit of
the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then
the serial number is entered. After the 48th bit of the serial number has been entered, the Shift Register
contains the CRC value.
DS2751
14 of 19
Figure 12. 1-WIRE CRC GENERATION BLOCK DIAGRAM
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the
bus with open-drain or tri-state output drivers. The DS2751 uses an open-drain output driver as part of the
bidirectional interface circuitry shown in Figure 13. If a bidirectional pin is not available on the bus
master, separate output, and input pins can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the
value of this resistor should be approximately 5kW. The idle state for the 1-Wire bus is high. If, for any
reason, a bus transaction must be suspended, the bus must be left in the idle state in order to properly
resume the transaction later. If the bus is left low for more than 120ms, slave devices on the bus begin to
interpret the low period as a reset pulse, effectively terminating the transaction.
Figure 13. 1-WIRE BUS INTERFACE CIRCUITRY
TRANSACTION SEQUENCE
The protocol for accessing the DS2751 through the 1-Wire port is as follows:
§ Initialization
§ Net Address Command
§ Function Command
§ Transaction/Data
The sections that follow describe each of these steps in detail.
1mA
Typ.
100W
MOSFET
Tx
Rx Rx
Tx
Rx = RECEIVE
Tx = TRANSMIT
V
PULLUP
(2.0V to 5.5V)
4.7kW
BUS MASTER DS2751 1-WIRE PORT
MSb
XOR
XOR
LSb
XOR
INPUT
DS2751
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All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse
transmitted by the bus master followed by a presence pulse simultaneously transmitted by the DS2751
and any other slaves on the bus. The presence pulse tells the bus master that one or more devices are on
the bus and ready to operate. For more details, see the I/O Signaling section.
NET ADDRESS COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the net address
commands described in the following paragraphs. The name of each ROM command is followed by the
8-bit opcode for that command in square brackets. Figure 14 presents a transaction flowchart of the net
address commands.
Read Net Address [33h or 39h]. This command allows the bus master to read the DS2751’s 1-Wire net
address. This command can only be used if there is a single slave on the bus. If more than one slave is
present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a
wired-AND result). The RNAOP bit in the Status Register selects the opcode for this command, with
RNAOP = 0 indicating 33h and RNAOP = 1 indicating 39h.
Match Net Address [55h]. This command allows the bus master to specifically address one DS2751 on
the 1-Wire bus. Only the addressed DS2751 responds to any subsequent function command. All other
slave devices ignore the function command and wait for a reset pulse. This command can be used with
one or more slave devices on the bus.
Skip Net Address [CCh]. This command saves time when there is only one DS2751 on the bus by
allowing the bus master to issue a function command without specifying the address of the slave. If more
than one slave device is present on the bus, a subsequent function command can cause a data collision
when all slaves transmit data at the same time.
Search Net Address [F0h]. This command allows the bus master to use a process of elimination to
identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the
repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired
value of that bit. The bus master performs this simple three-step routine on each bit location of the net
address. After one complete pass through all 64 bits, the bus master knows the address of one device. The
remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the Book
of DS19xx i
Button
®
Standards for a comprehensive discussion of a net address search, including an actual
example. This publication can be found on the Maxim/Dallas website at www.maxim-ic.com
.
FUNCTION COMMANDS
After successfully completing one of the net address commands, the bus master can access the features of
the DS2751 with any of the function commands described in the following paragraphs. The name of each
function is followed by the 8-bit opcode for that command in square brackets.
Read Data [69h, XX]. This command reads data from the DS2751 starting at memory address XX. The
LSb of the data in address XX is available to be read immediately after the MSb of the address has been
entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb
of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX.
If the bus master continues to read beyond address FFh, the DS2751 outputs logic 1 until a reset pulse
occurs. Addresses labeled “reserved” in the memory map contain undefined data. The Read Data
command can be terminated by the bus master with a reset pulse at any bit boundary.
iButton is a registered trademark of Dallas Semiconductor.

DS2751E+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Battery Management
Lifecycle:
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