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AD7621ASTZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
AD7621
Rev. 0 | Page 9 of 32
Pin No. Mnemonic Type
1
Description
14 D5 DI/O
When SER/
PAR = low this output is used as Bit 5 of the parallel port data output bus.
or INVSYNC
When SER/
PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15 D6 DI/O
When SER/
PAR
= low this output is used as Bit 6 of the parallel port data output bus.
or INVSCLK Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal.
16 D7 DI/O Bit 7 of the Parallel Port Data Output Bus.
or RDC
When SER/
PAR = high, read during convert. When using Serial Master mode (EXT/INT = low), RDC is
used to select the read mode.
When RDC = high, the previous conversion result is read during current conversion and the period of
SCLK changes (see the
Master Serial Interface section).
When RDC = low (read after convert), the current result is read after conversion.
or SDIN
Serial Data In. When using serial slave mode, (EXT/
INT = high), SDIN could be used as a data input to
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read
sequence.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
(2.5 V or 3 V).
19 DVDD P Digital Power. Nominally at 2.5 V.
20 DGND P Digital Power Ground.
21 D8 DO
When SER/
PAR = low this output is used as Bit 8 of the parallel port data output bus.
or SDOUT
When SER/
PAR = high, serial data output. In serial mode, this pin is used as the serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C.
In master mode (EXT/
INT = low). SDOUT is valid on both edges of SCLK.
In slave mode (EXT/
INT = high):
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22 D9 DI/O
Parallel Port Data Output Bus Bit 9. When SER/
PAR = low, this output is used as Bit 9 of the parallel port
data output bus.
or SCLK
Serial Clock. When SER/
PAR = high, serial clock. In all serial modes, this pin is used as the serial data
clock input or output, dependent upon the logic state of the EXT/
INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23 D10 DO
When SER/
PAR = low, this output is used as Bit 10 of the parallel port data output bus.
or SYNC
When SER/
PAR = high, frame synchronization. In serial master mode (EXT/INT= low), this output is
used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while
SDOUT output is valid.
24 D11 DO
Parallel Port Data Output Bus Bit 11. When SER/
PAR = low, this output is used as Bit 11 of the parallel
port data output bus.
or RDERROR
Read Error. When SER/
PAR = high, read error. In serial slave mode (EXT/INT = high), this output is used
as an incomplete read error flag. If a data read is started and not completed when the current
conversion is complete, the current data is lost and RDERROR is pulsed high.
25 to 28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus.
29 BUSY DO
Busy Output. Transitions high when a conversion is started, and remains high until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used
as a data ready clock signal.
30 DGND P Digital Power Ground.
31
RD
DI
Read Data. When
CS and RD are both low, the interface parallel or serial output bus is enabled.
AD7621
Rev. 0 | Page 10 of 32
Pin No. Mnemonic Type
1
Description
32
CS
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS
is
also used to gate the external clock in slave serial mode.
33 RESET DI
Reset Input. When high, reset the AD7621. Current conversion if any is aborted. Falling edge of RESET
enables the calibration mode indicated by pulsing BUSY high. Refer to the
Digital Interface section. If
not used, this pin can be tied to DGND.
34 PD DI
Power-Down Input. When high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
35
CNVST
DI
Conversion Start. A falling edge on
CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
36 AGND P Analog Power Ground Pin.
37 REF AI/O
Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the
Voltage Reference Input section.
38 REFGND AI Reference Input Analog Ground.
39 IN− AI Differential Negative Analog Input.
43 IN+ AI Differential Positive Analog Input.
45 TEMP AO Temperature Sensor Analog Output.
46 REFBUFIN AI/O
Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V
(typical) bandgap output on this pin, which needs external decoupling. The internal fixed gain
reference buffer uses this to produce 2.048V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the
Voltage Reference Input section.
47 PDREF DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
48 PDBUF DI
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
1
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
AD7621
Rev. 0 | Page 11 of 32
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full-scale through positive full-
scale. The point used as negative full-scale occurs ½ LSB before
the first code transition. Positive full-scale is defined as a level
1½ LSBs beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal negative full-scale
(−2.0479688 V for the ±2.048 V range). The last transition
(from 111…10 to 111…11) should occur for an analog voltage
1½ LSBs below the nominal full-scale (2.0479531 V for the
±2.048 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Dynamic Range
Dynamic range is the ratio of the rms value of the full-scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINAD
dB
− 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance
measured from the falling edge of the
CNVST
input to when
the input signal is held for a conversion.
Transient Response
The time required for the AD7621 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (V
REF
)
measured at T
MIN
, T(25°C), and T
MAX
. It is expressed in ppm/°C as
6
MINMAXREF
REFREF
REF
10
)T–T()25(V
)(V–)(V
)(TCV ×
×°
=°
C
Cppm/
MinMax
where:
V
REF
(Max) = maximum V
REF
at T
MIN
, T (25°C), or T
MAX
V
REF
(Min) = minimum V
REF
at T
MIN
, T (25°C), or T
MAX
V
REF
(25°C) = V
REF
at 25°C
T
MAX
= +85°C
T
MIN
= –40°C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

AD7621ASTZRL

Mfr. #:
Buy AD7621ASTZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16B 2LSB INL 3 MSPS
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