NB7L585MNR4G

NB7L585
http://onsemi.com
4
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT V
CC
= 2.375 V to 3.6 V; GND = 0 V; T
A
= −40°C to 85°C
(Note 5)
Symbol
Characteristic Min Typ Max Unit
POWER SUPPLY
V
CC
Power Supply Voltage V
CC
= 3.3V
V
CC
= 2.5V
3.0
2.375
3.3
2.5
3.6
2.625
V
I
CC
Power Supply Current (Inputs and Outputs Open) 185 225 mA
LVPECL Outputs
V
OH
Output HIGH Voltage (Note 6)
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
– 1145
2155
1355
V
CC
– 800
2500
1700
mV
V
OL
Output LOW Voltage (Note 6)
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
– 2000
1300
500
V
CC
– 1500
1800
1000
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 5 & 6)
V
IH
Single−ended Input HIGH Voltage V
th
+ 100 V
CC
mV
V
IL
Single−ended Input LOW Voltage GND V
th
− 100 mV
V
th
Input Threshold Reference Voltage Range (Note 8) 1100 V
CC
−100 mV
V
ISE
Single−ended Input Voltage (V
IH
− V
IL
) 200 1200 mV
VREFACx (for Capacitor− Coupled Inputs, Only)
V
REFAC
Output Reference Voltage @100 mA for Capacitor− Coupled
Inputs, Only
V
CC
– 1500 V
CC
– 1200 V
CC
– 1000 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 8) (Note 9)
V
IHD
Differential Input HIGH Voltage (IN, IN) 1200 V
CC
mV
V
ILD
Differential Input LOW Voltage (IN , IN) GND V
IHD
− 100 mV
V
ID
Differential Input Voltage (IN , IN) (V
IHD
− V
ILD
) 100 1200 mV
V
CMR
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
1050 V
CC
− 50 mV
I
IH
Input HIGH Current IN/IN (VTIN/VTIN Open) −150 150
mA
I
IL
Input LOW Current IN/IN (VTIN/VTIN Open) −150 150
mA
CONTROL INPUT (SEL Pin)
V
IH
Input HIGH Voltage for Control Pin 2.0 V
CC
mV
V
IL
Input LOW Voltage for Control Pin GND 0.8 mV
I
IH
Input HIGH Current −150 150
mA
I
IL
Input LOW Current −150 150
mA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor (Measured from INx to VTx) 45 50 55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. LVPECL outputs (Qn/Qn
) loaded with 50 W to V
CC
– 2 V for proper operation.
7. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10.V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
NB7L585
http://onsemi.com
5
Table 6. AC CHARACTERISTICS V
CC
= 2.375 V to 3.6 V; GND = 0 V; T
A
= −40°C to 85°C (Note 11)
Symbol
Characteristic Min Typ Max Unit
f
MAX
Maximum Input Clock Frequency; V
OUTpp
w 400 mV 5 7 GHz
f
DATAMAX
Maximum Operating Data Rate (PRBS23) 8 10 Gbps
f
SEL
Maximum Toggle Frequency, SEL 1.0 1.5 GHz
V
OUTpp
Output Voltage Amplitude (@ V
INPPmin
) f
in
4 GHz
(Note 12) (Figures 8 and 10) f
in
5 GHz
550
400
800
650
mV
t
PLH
,
t
PHL
Propagation Delay to Differential Outputs, @ 1 GHz,
measured at differential crosspoint
IN/IN to Q/Q
SEL to Q
125
75
175
200
250
300
ps
t
PLH
TC Propagation Delay Temperature Coefficient 50
Dfs/°C
tskew Output − Output skew (within device) (Note 13)
Device − Device skew (tpd max – tpdmin)
20
100
ps
t
DC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) f
in
v 5.0 GHz 45 50 55 %
F
N
Phase Noise, f
in
= 1 GHz 10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
−135
−137
−149
−150
−150
−151
dBc
t
ŐF
N
Integrated Phase Jitter (Figure x) fin = 1 GHz, 12 kHz * 20 MHz Offset (RMS) 36 fs
t
JITTER
RJ – Output Random Jitter (Note 14) f
in
5.0 GHz
DJ − Residual Output Deterministic Jitter (Note 15) 8 Gbps
0.2
5
0.8
15
ps rms
ps pk−pk
Crosstalk Induced Jitter (Adjacent Channel) (Note 17) 0.7 psRMS
V
INPP
Input Voltage Swing (Differential Configuration) (Note 16) 100 1200 mV
t
r,
, t
f
Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q 25 55 85 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV pk−pk source, 50% duty cycle clock source. All output loading with external 50 W to V
CC
– 2 V. Input edge
rates 40 ps (20% − 80%).
12.Output voltage swing is a single−ended measurement operating in differential mode.
13.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16.Input voltage swing is a single−ended measurement operating in differential mode.
17.Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
f
in
, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Clock Output Voltage Amplitude (V
OUTpp
) vs. Input Frequency (f
in
) at Ambient Temperature (Typical)
OUTPUT VOLTAGE AMPLITUDE
(mV)
0
200
1000
01 8765423
Q AMP (mV)
800
600
400
NB7L585
http://onsemi.com
6
Figure 4. Input Structure
Figure 5. Differential Input Driven Single−Ended
Figure 6. V
th
Diagram Figure 7. Differential Inputs Driven Differentially
Figure 8. Differential Inputs Driven Differentially
Figure 9. VCMR Diagram
Figure 10. AC Reference Measurement
V
IHD
V
ILD
V
ID
= |V
IHD(IN)
− V
ILD(IN)
|
IN
IN
IN
V
th
IN
IN
IN
IN
IN
Q
Q
t
PLH
t
PHL
V
INPP
= V
IH
(IN) − V
IL
(IN)
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
50 W
50 W
INx
VTx
INx
V
CC
V
EE
V
thmin
V
thmax
V
th
IN
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
V
EE
V
CMRmin
V
CMRmax
V
CMR
IN
IN
V
IHDmax
V
ILDmax
V
ID
= V
IHD
− V
ILD
V
IHDtyp
V
ILDtyp
V
IHDmin
V
ILDmin
V
th
V
IH
V
IL
Figure 11. SEL to Qx Timing Diagram
tpd tpd
V
CC
/ 2 V
CC
/ 2
SEL
Qx
Qx

NB7L585MNR4G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution 2.5/3.3V DIFF MUX
Lifecycle:
New from this manufacturer.
Delivery:
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